Bus Structure

A system bus is the set of shared electrical signal paths that interconnects the CPU, main memory and I/O controllers. A complete transfer uses address lines to select a source or destination, control lines to specify the operation and timing, and data lines to carry the value.

The functional arrangement is shown in the figure. A modern computer may replace one physical shared bus by several point-to-point links, but the logical address, data and control functions remain.

Address, Data and Control Buses

Bus	Normal direction	Information carried	Width or control significance
Address	Usually CPU $\rightarrow$ memory/I/O	Binary address of a memory location or I/O port	With $n$ address lines, at most $2^n$ distinct locations can be selected.
Data	Bidirectional	Instruction words, operands, device data and results	An $m$-bit data bus carries at most $m$ bits per transaction; wider paths need more pins and traces.
Control	Mixed direction	Read, write, clock, reset, ready/wait, bus request/grant and interrupt request/acknowledge	Establishes the bus master, operation, synchronization and completion; it has no single fixed direction.

Logical groups within a system bus.

The address bus is commonly unidirectional because the CPU or another current bus master initiates the transaction. The data bus must reverse direction between a read and a write. Control direction depends on the signal: an interrupt request travels toward the CPU, while interrupt acknowledge travels back to the requesting controller.

Caution

Key Formula — Addressable capacity

For $n$ address lines,

$$N_{locations}=2^n.$$

If the system is byte-addressable, its directly addressable capacity is $2^n$ bytes. In a word-addressable system, multiply by the bytes per word.

Bus Read and Write Operations

1. Memory read: the CPU places the required address on the address bus and asserts memory read. The selected memory decodes the address, drives the requested value onto the data bus and may assert ready. The CPU samples the value and then removes the request.

2. Memory write: the CPU places the destination address on the address bus and the new value on the data bus, then asserts memory write. The selected memory stores the value and signals completion; the CPU then releases the buses.

Only one device should drive a shared data bus at a time. Address decoding and bus-enable control prevent electrical contention. If a device is slower than the nominal cycle, a ready/wait handshake inserts wait states.

Note

Example — Sixteen-bit address bus

A byte-addressable processor with 16 address lines selects

$$2^{16}=65{,}536\ \text{bytes}=\boxed{64\ \text{KiB}}.$$

If the external data bus is 8 bits wide, one byte moves per transaction. A 32-bit word therefore requires four data transactions unless a wider interface or burst mechanism is available. The 16-bit address width sets the number of addresses; it does not mean that 16 data bits move at once.

Timing, Arbitration and Performance

A synchronous bus relates transfers to a shared clock. It is simple and fast when devices have compatible timing. An asynchronous bus uses request/acknowledge handshaking and can accommodate devices of different speeds, at the cost of control overhead.

When the CPU, DMA controller or another agent can initiate a transaction, arbitration grants ownership to one requester. Bus request/grant lines, priority and fairness rules ensure that two masters do not transmit simultaneously and that a low-priority requester is not indefinitely denied.

An ideal peak data rate for one transfer per clock is

$$R_{peak}=\frac{m}{8}f\quad\text{bytes/s},$$

where $m$ is data-bus width in bits and $f$ is bus frequency. This is an upper bound: arbitration delay, protocol overhead, wait states, electrical loading and shared-bus contention reduce sustained throughput. Bus width alone does not determine computer performance.

Bus Classification

Type	Description	Examples or remarks
Internal bus	Connects registers, ALU, control and other units inside the CPU	Processor data path and internal control paths
System bus	Connects CPU, memory and I/O controllers	Logical address, data and control groups; memory bus
Expansion bus	Attaches peripheral or add-in controllers	PCI Express and legacy PCI
Parallel bus	Sends several bits simultaneously over several conductors	Short memory channels and legacy parallel interfaces
Serial bus	Sends ordered bits over one or a few lanes	PCIe, USB, SATA, I²C and SPI

Bus classifications and examples.

Parallel links spend pins and board area to move many bits at once, but skew between conductors limits distance and high-speed scaling. Serial links use fewer conductors and can run at high symbol rates; multiple serial lanes may be combined for throughput. the section compares their timing and applies the distinction to RS-232.

Quick Review

• Address: selects one of $2^n$ locations with $n$ lines.

• Data: moves instructions, operands and results in either direction.

• Control: specifies read/write, ownership, timing, readiness, reset and interrupts.

• Transaction: address plus command first, controlled data transfer second, completion last.

Tip

Exam Focus — Bus answer

Draw CPU, memory and I/O around three labeled bus groups. State each group’s direction and function, derive $2^n$, and describe both read and write cycles. Finish by noting that control lines are mixed-direction and that practical throughput is below the width–frequency peak.