Sequential Logic

A sequential circuit contains memory. Its next state depends on present inputs and the stored present state. A latch is level-sensitive; a flip-flop updates on a clock edge.

Let $Q_n$ denote the state before the active event and $Q_{n+1}$ or $Q^+$ the state after it.

Latches

Active-HIGH SR latch

Two cross-coupled NOR gates form an active-HIGH set–reset latch. Feedback makes the circuit bistable: after an input pulse ends, the new state remains.

Active-HIGH SR latch made from cross-coupled NOR gates. The feedback paths retain the state after $S$ or $R$ returns LOW.

$S$	$R$	$Q^+$	Operation
	0	$Q$	hold
0	1	0	reset
1	0	1	set
1	1	undefined	forbidden

Active-HIGH NOR SR-latch operation.

For the valid input combinations,

$$\boxed{Q^+=S+\overline RQ},\qquad SR=0.$$

When $S=R=1$, both NOR outputs are forced LOW. Releasing both inputs together can leave the final state dependent on unequal gate delays, so this command is forbidden. A cross-coupled NAND latch instead uses active-LOW inputs and has its forbidden condition at $\overline S=\overline R=0$.

A gated SR latch accepts $S$ and $R$ only while enable $E$ is active. A D latch removes the forbidden data combination by applying $S=D$ and $R=\overline D$ through the enable gates. While enabled it is transparent; when disabled it holds the last value.

Flip-Flops

A flip-flop samples its inputs only around the active clock edge. A triangle at the clock pin denotes edge triggering; a clock bubble plus triangle denotes a falling-edge device.

Positive- and negative-edge D and JK flip-flop symbols.

Type	Input 1	Input 2	Next state $Q^+$	Operation
SR			$Q$	hold
SR				reset
SR				set
SR			undefined	forbidden
JK			$Q$	hold
JK				reset
JK				set
JK			$\overline Q$	toggle
D		–		store 0
D		–		store 1
T		–	$Q$	hold
T		–	$\overline Q$	toggle

Characteristic behavior of standard flip-flops.

The characteristic equations are

$$\begin{aligned} \text{SR:}\quad &Q^+=S+\overline RQ, &&SR=0, \\ \text{JK:}\quad &Q^+=J\overline Q+\overline KQ, \\ \text{D:}\quad &Q^+=D, \\ \text{T:}\quad &Q^+=T\oplus Q. \end{aligned}$$

JK removes the SR forbidden command by making $J=K=1$ toggle. D is the natural storage element for registers and pipelines. T is convenient for counters and divides clock frequency by two when held at 1.

Excitation table

An excitation table works backward from a required state transition to the input that causes it. $\times$ denotes a don’t-care.

$Q$	$Q^+$	$S$	$R$	$J$	$K$	$D$	$T$
			$\times$		$\times$
					$\times$
				$\times$
		$\times$		$\times$

Combined flip-flop excitation table.

Use this table for counter and state-machine design: write present and next states, obtain each flip-flop input, simplify those input functions, then verify legal and unused states.

Triggering

Method	When state may respond	Main point
Level-sensitive latch	Throughout the active enable level	Can be transparent
Positive-edge flip-flop	Near the LOW-to-HIGH clock transition	One sample per rising edge
Negative-edge flip-flop	Near the HIGH-to-LOW clock transition	One sample per falling edge
Master–slave	Master and slave use opposite levels	External output changes once per cycle

Level and edge control compared.

Race-around and master–slave JK

A level-sensitive JK latch with $J=K=1$ feeds each output change back while the clock remains active. If the active pulse exceeds the feedback round-trip delay, $Q$ can toggle repeatedly; this is race-around.

Master–slave JK structure and suppression of external race-around.

The master is transparent during one clock level and the slave during the opposite level. The slave therefore receives one fixed master state and the external output changes once per cycle. A true edge-triggered flip-flop is the usual modern solution.

Setup, hold and clock-to-output delay

• Setup time $t_{su}$: data must be stable for this interval before the active edge.

• Hold time $t_h$: data must remain stable for this interval after the active edge.

• Clock-to-$Q$ delay $t_{CQ}$: time from the active edge until the output is valid.

Violating setup or hold can place the storage element in metastability: the output may take an unpredictable time to settle. An asynchronous input should normally pass through a synchronizer before entering synchronous logic.

For a register-to-register path, a basic single-clock timing condition is

$$\boxed{T_{clk}\ge t_{CQ(\max)}+t_{logic(\max)}+t_{su}+t_{skew}},$$

with a separate minimum-delay check for hold time.

Flip-Flop Applications

Element	Typical use
SR latch	set/reset control, switch debouncing, simple asynchronous memory
D latch	gated data storage and latch-based timing
D flip-flop	registers, pipelines, synchronizers and state machines
JK flip-flop	counters and flexible state control
T flip-flop	divide-by-two stages and binary counters

Natural applications of each storage type.

Note

Key Point — Sequential design discipline

State the active clock edge and asynchronous-input polarity, derive next-state logic from a state table, and verify setup, hold and unused-state behavior. Logic correctness alone does not guarantee a reliable clocked circuit.