Memory

Memory Fundamentals

A semiconductor memory is an addressable array of cells, each storing one bit. Cells are grouped into words; an applied address selects one word for a read or write through decoders, sense/write circuits and data buffers.

Term	Meaning
Memory cell	Smallest element; stores one bit ($0$ or $1$)
Word / word length	Bits accessed together; $m$ = bits per word
Memory array	Matrix of cells arranged in rows and columns
Address lines	$n$ inputs that select a word; $n$ lines address $2^{n}$ words
Data lines	$m$ bidirectional lines carrying one word in or out
Control lines	$\overline{CS}$ (chip select), $R/\overline{W}$ (read/write), $\overline{OE}$ (output enable)

Classification

Semiconductor memory types

• Volatile memory (RAM) loses data when power is removed.

• Non-volatile memory (ROM family) retains data without power.

• Read/write memory allows both operations in normal use; read-mostly memory (EPROM, EEPROM, Flash) is programmed by a separate, slower operation.

Memory Organization

Memory organization

• The row decoder activates one word line selected by the address.

• The column decoder with sense and write circuits picks the addressed bits and reads or drives them.

• Data buffers connect the selected word to the external data bus.

• The control logic sequences the access from $\overline{CS}$, $R/\overline{W}$ and $\overline{OE}$.

Control line	Active	Function
$\overline{CS}$	LOW	Enables the chip; a deselected chip ignores the bus
$R/\overline{W}$	—	HIGH $=$ read, LOW $=$ write
$\overline{OE}$	LOW	Connects the data buffers to the bus during a read

Memory Capacity

$$\boxed{N = 2^{\,n}}, \qquad \boxed{C = N \times m}, \qquad \boxed{n = \lceil \log_2 N \rceil},$$

where $N$ is the number of words, $m$ the bits per word and $n$ the number of address lines.

Word organizations

Note

Example — Capacity and address width

A $2\text{K} \times 8$ memory has

$$N = 2048 = 2^{11}, \qquad C = 2048 \times 8 = 16384\ \text{bits} = 2\ \text{KiB}.$$

It needs 11 address lines and 8 data lines.

Read Operation

1. Place the word address on the address lines.

2. Assert $\overline{CS}$ and set $R/\overline{W} = 1$ (read).

3. Assert $\overline{OE}$; after the access time $t_{AA}$ the addressed word appears on the data lines.

Read-cycle timing

Write Operation

1. Place the word address on the address lines.

2. Place the data word on the data lines.

3. Assert $\overline{CS}$ and pulse $R/\overline{W} = 0$ (write); the data is latched on the trailing edge of the write pulse.

Write-cycle timing

The data must be stable for the setup time $t_{DS}$ before and the hold time $t_{DH}$ after the latching edge; $t_{WP}$ is the minimum write-pulse width.

Random-Access Memory (RAM)

Random-access memory is volatile read/write memory in which any location is accessed directly in approximately the same time, independent of its address. It holds active programs and data while power is applied.

RAM has two forms that differ in how one bit is stored: SRAM uses a bistable latch, DRAM uses charge on a capacitor.

Static RAM (SRAM)

6T SRAM cell

• Storage: two cross-coupled inverters form a latch that holds the bit while power is present — a 6-transistor (6T) cell (4 latch $+$ 2 access transistors).

• Write: drivers force $BL$ and $\overline{BL}$ to the wanted levels, then $WL$ is asserted to overwrite the latch.

• Read: $BL$ and $\overline{BL}$ are precharged; asserting $WL$ develops a small differential that a sense amplifier resolves. The read is non-destructive.

• Refresh: not required while powered.

• Advantages: fast, no refresh. Disadvantages: low density, high cost per bit. Applications: cache, register files, buffers.

Dynamic RAM (DRAM)

1T1C DRAM cell

• Storage: one access transistor and one capacitor — a 1T1C cell. A charged $C_S$ is $1$, a discharged $C_S$ is $0$.

• Write: $WL$ turns the transistor on and $BL$ charges or discharges $C_S$.

• Read: connecting $C_S$ to the precharged bit line causes charge sharing; a sense amplifier detects the small change and restores the level. The read is destructive, so the cell is rewritten after every read.

• Refresh: leakage discharges $C_S$, so every row is refreshed periodically. If $N_r$ rows are refreshed within $T_R$,

$$\boxed{t_{row} = \frac{T_R}{N_r}}.$$

• Advantages: high density, low cost per bit. Disadvantages: refresh overhead, slower, destructive read. Applications: main memory.

SRAM vs DRAM

Parameter	SRAM	DRAM
Cell	6T bistable latch	1T1C charge cell
Storage	Flip-flop	Capacitor
Refresh	Not required	Required
Read	Non-destructive	Destructive (restore follows)
Speed	Faster	Slower
Density	Lower	Higher
Cost per bit	Higher	Lower
Main use	Cache	Main memory

Read-Only Memory (ROM)

Read-only memory is non-volatile memory whose contents are fixed during manufacture or written once by programming. In normal operation it is read but not written, and it retains data without power.

Two-word MOS ROM

Each selected word line reads out a fixed pattern: a cell with a transistor pulls its bit line LOW ($0$), while a cell without one stays HIGH ($1$). The stored data is the pattern of present and absent cells.

Type	Programming	Erasure
Mask ROM	During fabrication	Not erasable
PROM	Once, by the user (blow fuses)	Not erasable
EPROM	Electrical, floating-gate	UV light, whole chip
EEPROM	Electrical	Electrical, per byte
Flash	Electrical	Electrical, per block

PROM

PROM fuse cells

• Programmable ROM is supplied blank and is programmed once by the user, who irreversibly blows selected fusible links (or forms antifuses).

• An intact link conducts and reads one logic value; a blown link is open and reads the other. Once programmed it cannot be erased.

• Applications: permanent low-volume firmware and lookup data.

EPROM

EPROM cell and package

• Erasable PROM stores each bit as charge trapped on a floating gate. Programming injects electrons with a high voltage, raising the transistor threshold to store a $0$.

• Erasure exposes the chip to ultraviolet light through a quartz window, which frees the trapped charge and clears the whole chip back to $1$s.

• It can then be reprogrammed.

EPROM erase cycle

• Applications: development firmware and reprogrammable fixed data.

ROM vs RAM

Parameter	RAM	ROM
Operation	Read and write	Read (write only by programming)
Volatility	Volatile	Non-volatile
Data retention	Lost on power-off	Retained without power
Contents set	At run time	At manufacture or programming
Main use	Working memory	Firmware, fixed data

Memory Comparison

Feature	RAM	SRAM	DRAM	ROM	PROM	EPROM
Read	$\checkmark$	$\checkmark$	$\checkmark$	$\checkmark$	$\checkmark$	$\checkmark$
Write (normal)	$\checkmark$	$\checkmark$	$\checkmark$	$\times$	once	$\times$
Volatile	$\checkmark$	$\checkmark$	$\checkmark$	$\times$	$\times$	$\times$
Refresh	—	$\times$	$\checkmark$	—	—	—
Erasable	—	—	—	$\times$	$\times$	$\checkmark$ (UV)
Relative speed	—	High	Lower	—	—	—

PROM vs EPROM

Parameter	PROM	EPROM
Programmable	Once	Many times
Erasable	No	Yes, by UV light
Storage mechanism	Fuse / antifuse link	Floating-gate charge
Package	Standard	Quartz window
Reusable	No	Yes

Memory Numericals

$$\boxed{\text{Number of locations} = 2^{\,\text{address lines}}}, \qquad \boxed{\text{Capacity} = \text{locations} \times \text{bits per word}}.$$

Note

Example 1 — $2^{10} \times 8$ memory

$$\text{address lines} = 10, \quad \text{locations} = 2^{10} = 1024, \quad m = 8,$$$$C = 1024 \times 8 = 8192\ \text{bits} = 1\ \text{KiB}.$$

[!NOTE]

Example 2 — Address and data width from capacity

A $4\text{K} \times 16$ memory:

$$N = 4096 = 2^{12} \Rightarrow 12\ \text{address lines}, \quad m = 16\ \text{data lines},$$$$C = 4096 \times 16 = 65536\ \text{bits} = 8\ \text{KiB}.$$

[!NOTE]

Example 3 — Locations from address lines

With 16 address lines and an 8-bit word,

$$N = 2^{16} = 65536, \quad C = 65536 \times 8 = 524288\ \text{bits} = 64\ \text{KiB}.$$

Quick Review

• Capacity: $N = 2^{\,n}$ words and $C = N \times m$ bits.

• SRAM: 6T latch, no refresh, fast, low density — cache.

• DRAM: 1T1C charge cell, destructive read, needs refresh, high density — main memory.

• ROM: non-volatile; stores a fixed pattern of present and absent cells.

• PROM: programmed once by blowing fuses; not erasable.

• EPROM: floating-gate storage; UV-erasable through a quartz window and reprogrammable.