Adder Model Answers

Half Adder

Definition and Block Diagram

• A half adder is a combinational logic circuit that adds two single-bit binary numbers.

• It produces two outputs: a Sum ($S$) and a Carry ($C$).

• It has no carry input, so it can directly add only the two least-significant bits.

Half adder block diagram

Truth Table

$A$	$B$	$S$	$C$
	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

For $1+1$ the result is $10_2$, so the sum bit is $0$ and the carry bit is $1$.

Boolean Expressions (K-Map Derivation)

Half adder Karnaugh maps for the sum and carry outputs

The two isolated $1$s of the sum map cannot be grouped, which gives an XOR; the single $1$ of the carry map gives an AND:

$$S=\overline{A}B+A\overline{B}=A\oplus B$$ $$\boxed{\,S=A\oplus B\,},\qquad \boxed{\,C=AB\,}$$

Logic Circuit Diagram

Half adder logic circuit using an XOR gate and an AND gate

• An XOR gate driven by $A$ and $B$ produces the sum $S=A\oplus B$.

• An AND gate driven by the same $A$ and $B$ produces the carry $C=AB$.

Limitation and Applications

• Limitation: it cannot accept a carry-in ($C_{in}$) from a previous stage, so by itself it cannot add multi-bit numbers beyond the least-significant bit.

• Applications:

  • Building block of the full adder (two half adders and an OR gate).

  • Least-significant-bit position of ripple-carry adders.

  • Arithmetic in calculators, ALUs, and address-decoding logic.

Full Adder

Definition and Block Diagram

• A full adder is a combinational logic circuit that adds three single-bit inputs: $A$, $B$, and a carry-in $C_{in}$.

• It produces two outputs: a Sum ($S$) and a Carry-out ($C_{out}$).

• Unlike the half adder, it accounts for the carry generated by a lower-order stage.

Full adder block diagram

Truth Table

$A$	$B$	$C_{in}$	$S$	$C_{out}$
	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

K-Map Derivation and Boolean Expressions

Sum ($S$)

Full adder Karnaugh map for the sum output

The $1$s form a checkerboard, so no cells can be grouped:

$$S=\overline{A}\,\overline{B}\,C_{in}+\overline{A}B\overline{C}_{in} +A\overline{B}\,\overline{C}_{in}+ABC_{in}$$ $$\boxed{\,S=A\oplus B\oplus C_{in}\,}$$

Carry-out ($C_{out}$)

Full adder Karnaugh map for the carry-out output

The three overlapping pairs give the standard SOP form:

$$\boxed{\,C_{out}=AB+BC_{in}+AC_{in}\,}$$

An implementation-friendly form using the first half adder’s XOR is:

$$C_{out}=AB+C_{in}(A\oplus B)$$

Logic Circuit Diagrams

Method 1 — Basic gates (direct SOP)

Full adder using a three-input XOR, three AND gates, and a three-input OR gate

• A 3-input XOR on $A$, $B$, $C_{in}$ gives the sum $S$.

• Three AND gates form $AB$, $BC_{in}$, $AC_{in}$, and a 3-input OR combines them into $C_{out}$.

Method 2 — Two half adders and an OR gate

Full adder built from two half adders and an OR gate

• HA$_1$ adds $A$ and $B$: $S_1=A\oplus B$ and $C_1=AB$.

• HA$_2$ adds $S_1$ and $C_{in}$: $S=S_1\oplus C_{in}$ and $C_2=C_{in}S_1$.

• An OR gate combines the carries: $C_{out}=C_1+C_2$.

Applications

• Cascaded to form parallel adders (ripple-carry and carry-lookahead) that add multi-bit numbers in 8-, 16-, and 32-bit CPUs.

• Core of the arithmetic logic unit (ALU) in microprocessors.

• Used in address generation and multiplier circuits.