Logic Families

A logic family is a set of digital circuits made with one device technology and designed to have compatible supply voltages, logic levels, input/output currents, delay and loading limits.

Parameters Used to Compare Families

Parameter	Meaning
$V_{IL(\max)}$	Largest input voltage guaranteed to be interpreted as LOW
$V_{IH(\min)}$	Smallest input voltage guaranteed to be interpreted as HIGH
$V_{OL(\max)}$	Largest guaranteed LOW output voltage at rated sink current
$V_{OH(\min)}$	Smallest guaranteed HIGH output voltage at rated source current
Fan-in	Number of inputs provided by one gate; larger fan-in usually increases delay
Fan-out	Maximum compatible inputs that one output can drive in both logic states
$t_{PLH},t_{PHL}$	Output LOW-to-HIGH and HIGH-to-LOW propagation delays
$P_D$	Average power dissipated by one gate under stated static and switching conditions
Noise margin	Allowed unwanted voltage before a guaranteed output can be misread

Essential logic-family parameters.

The guaranteed noise margins are

$$\boxed{NM_H=V_{OH(\min)}-V_{IH(\min)}},\qquad \boxed{NM_L=V_{IL(\max)}-V_{OL(\max)}}.$$

For unequal edge delays, quote the average propagation delay

$$\boxed{t_{pd}=\frac{t_{PLH}+t_{PHL}}{2}}.$$

Transistor–Transistor Logic

Transistor–Transistor Logic (TTL) uses bipolar transistors for the input logic decision and for output amplification. The classic 74xx family uses a nominal $5\,V$ supply, and its natural primitive is NAND.

Standard TTL NAND gate

A two-input TTL NAND contains four functional blocks:

1. multi-emitter input transistor $Q_1$ for current steering;

2. phase splitter $Q_2$;

3. active pull-up $Q_3$ with a level-shift diode;

4. pull-down $Q_4$ in a totem-pole output.

Functional circuit of a standard two-input TTL NAND gate. The integrated multi-emitter device $Q_1$ is shown as a labelled current-steering block so its distinct emitter inputs remain legible.

Inputs	$Q_1$ current path	$Q_2$	Output stage	$Y$
Any input LOW	Current leaves through the LOW emitter	OFF	Pull-up ON, pull-down OFF
All inputs HIGH	Current reaches $Q_2$ through $Q_1$	ON	Pull-up OFF, pull-down saturated

Operation of the standard two-input TTL NAND.

With any LOW input, $Q_1$ diverts drive away from $Q_2$; the output rises. With all inputs HIGH, $Q_2$ drives the pull-down and removes pull-up drive; the output falls. Thus $Y=\overline{AB}$.

TTL NOR gate

TTL NOR cannot obtain its OR decision from one multi-emitter transistor. It uses a separate input/phase-splitter branch for each input and combines their collector and emitter actions before one output stage.

Transistor-level circuit of a two-input TTL NOR gate. Each input has its own current-steering transistor and phase splitter; the splitter collectors and emitters drive the shared $Q_6$–$Q_5$ totem-pole output.

$A$	$B$	Conducting phase splitter(s)	Pull-down	$Y$
		none	OFF
		$B$ branch	ON
		$A$ branch	ON
		both branches	ON

Two-input TTL NOR state summary.

Any HIGH input activates its branch, lowers the pull-up drive and turns on the common pull-down. NAND is therefore simpler and more economical in TTL.

TTL levels, loading and speed

Standard TTL uses guaranteed limits rather than typical values.

Parameter	Limit	Interpretation
$V_{IL(\max)}$	$0.8\,V$	valid input LOW at or below this value
$V_{IH(\min)}$	$2.0\,V$	valid input HIGH at or above this value
$V_{OL(\max)}$	$0.4\,V$	guaranteed output LOW at rated sink current
$V_{OH(\min)}$	$2.4\,V$	guaranteed output HIGH at rated source current

Guaranteed standard-TTL voltage limits.

the equation gives

$$NM_L=0.8-0.4=0.4\,V,\qquad NM_H=2.4-2.0=0.4\,V.$$

Guaranteed TTL input/output bands and the noise-margin construction.

A LOW TTL output sinks current; a HIGH output sources current. Using current magnitudes,

$$\boxed{FO_L=\frac{I_{OL(\max)}}{I_{IL(\max)}}},\qquad \boxed{FO_H=\frac{|I_{OH(\max)}|}{I_{IH(\max)}}},\qquad \boxed{FO=\min(FO_L,FO_H)}.$$

Note

Example — TTL fan-out

If an output can sink $16\,mA$ and source $0.4\,mA$, while each input requires $1.6\,mA$ LOW and $40\,\mu\mathrm{A}$ HIGH, then

$$FO_L=\frac{16}{1.6}=10,\qquad FO_H=\frac{400}{40}=10,$$

so the permitted fan-out is 10. Both states must pass.

TTL dissipates static power because bias current flows in either logic state. Deeply saturated BJTs also store charge. A Schottky clamp prevents the base–collector junction from becoming strongly forward biased, reducing storage delay. A common comparison measure is

$$\boxed{\mathrm{speed\text{-}power\ product}=P_Dt_{pd}},$$

with units of joules per switching event; lower is better for the stated test conditions.

NMOS Logic

NMOS logic uses enhancement NMOS transistors in a pull-down network and an always-conducting resistor or depletion-mode MOSFET as the pull-up load. The LOW level depends on the driver-to-load strength ratio.

In a depletion-load inverter the load gate is tied to its source, so $V_{GS,L}=0$. Its threshold is negative, hence it remains ON. The input controls the enhancement NMOS driver.

Depletion-load NMOS inverter $Y=\overline A$, NAND $Y=\overline{AB}$ with a series PDN, and NOR $Y=\overline{A+B}$ with a parallel PDN. Each load has its gate tied to source and is always conducting.

Gate	Pull-down network	LOW-output condition
Inverter	one controlled NMOS	$A=1$
NAND	NMOS devices in series	every input is 1
NOR	NMOS devices in parallel	any input is 1

NMOS primitive-gate operation.

When the driver is OFF, the load charges the output HIGH. When the driver is ON, load and driver conduct simultaneously; a sufficiently strong driver pulls the output LOW. Therefore

$$\boxed{P_{static,L}=V_{DD}I_{DD,L}>0}.$$

The pull-up is weaker than the active pull-down, so LOW-to-HIGH transitions are normally slower than HIGH-to-LOW transitions.

CMOS Logic

Complementary MOS (CMOS) combines a PMOS pull-up network (PUN) with an NMOS pull-down network (PDN). For every valid stable input, one network should connect the output to a supply rail while the other remains open.

An NMOS turns ON for a sufficiently HIGH gate voltage and naturally pulls toward ground. A PMOS turns ON for a sufficiently LOW gate voltage and naturally pulls toward $V_{DD}$.

CMOS inverter

CMOS inverter and its two stable current-path states.

$A$	PMOS	NMOS	$Y$	Ideal direct path $V_{DD}$–GND
	ON	OFF	($V_{DD}$)	open
	OFF	ON	(GND)	open

Static CMOS inverter states.

Near the switching voltage both devices conduct and the output changes steeply. The input thresholds $V_{IL}$ and $V_{IH}$ are conventionally taken where the voltage-transfer curve has slope $-1$.

Representative CMOS inverter VTC. The dashed line locates $V_I=V_O$; its intersection gives the switching point $V_M$.

The rail-to-rail output and steep transition usually give larger noise margins than standard TTL, but actual limits come from the device data sheet and supply voltage.

CMOS NAND and NOR

Build the NMOS PDN from the condition that must pull $Y$ LOW:

• AND condition $\rightarrow$ NMOS devices in series;

• OR condition $\rightarrow$ NMOS devices in parallel.

The PMOS PUN is the dual: replace NMOS by PMOS and interchange series with parallel.

Complementary two-input CMOS networks: NAND uses a parallel PMOS PUN and series NMOS PDN; NOR uses a series PMOS PUN and parallel NMOS PDN.

Gate	NMOS PDN	PMOS PUN
NAND $\overline{AB}$	$A$ and $B$ in series	$A$ and $B$ in parallel
NOR $\overline{A+B}$	$A$ and $B$ in parallel	$A$ and $B$ in series

Static-CMOS network rules.

For a complex gate, write the LOW condition $F_0=\overline Y$, draw the PDN for $F_0$, then draw its dual PUN. Verify every input row gives one complete rail path and never two stable rail paths.

CMOS delay and power

Gate inputs draw negligible steady DC current but add capacitance. Fan-out is therefore limited mainly by charging delay, dynamic energy and leakage rather than by a TTL-like input-current ratio. A first-order estimate is

$$t_{pHL}\approx0.69R_nC_L,\qquad t_{pLH}\approx0.69R_pC_L.$$

With switching activity $\alpha$ and event rate $f$,

$$\boxed{P_{total}\approx \alpha C_LV_{DD}^{2}f +V_{DD}I_{leak}+P_{sc}}.$$

$P_{sc}$ is the brief short-circuit component while both devices conduct during an edge. Supply reduction lowers dynamic power quadratically, but also reduces noise headroom and drive strength.

Note

Key Point — Never leave a CMOS input floating

A floating MOS gate can acquire an unpredictable voltage through leakage and capacitive coupling. Both networks may then conduct partially, producing an undefined output and excess current. Tie every unused input to a defined logic level.

CMOS, TTL and NMOS Compared

Property	TTL	NMOS	CMOS
Devices	Bipolar transistors	NMOS PDN plus always-on load	Complementary PMOS PUN and NMOS PDN
Input loading	Finite DC current	Mainly capacitive	Mainly capacitive
Static power	Bias current in both states	High when output is LOW	Ideally leakage only
Output swing	Not normally rail-to-rail	Ratio-dependent LOW	Nearly rail-to-rail
Fan-out limit	Source/sink current	Capacitance and ratio	Capacitance, delay and leakage
Noise margin	Modest, tightly specified	Ratio-dependent	Usually large
Typical role	Legacy 74xx control/interface	Historical processors	Dominant modern digital IC technology

Practical family comparison; exact values depend on sub-family and process.

Note

Key Point — Family selection checklist

Use guaranteed input/output limits, not typical voltages. Check both noise margins, both fan-out states, worst-case path delay, power at the intended switching activity, supply compatibility and the rule for unused inputs.