Analog-to-Digital Conversion

A digital-to-analog converter (DAC) maps an $n$-bit input word to a corresponding analog voltage or current. Its core generates one of finitely many analog levels; an output hold and reconstruction network may then form a continuous-time waveform.

Tip

Exam Focus — High-yield DAC answer

Define the transfer law and one LSB, draw the requested switch/resistor, capacitor or current-source network, derive its binary weights, and then distinguish resolution, accuracy, monotonicity, settling time and glitch impulse. End an architecture answer with merits, limitations and applications.

Conversion Chain and Fundamental Quantities

Complete DAC signal path. The core selects an analog level from a digital word and precision reference; buffering, zero-order hold and optional reconstruction filtering determine the delivered continuous-time waveform.

The complete signal path performs three distinct operations:

• Decode and switch: the registered digital word controls weighted analog elements referred to a precision voltage or current.

• Generate and buffer: the DAC core produces a voltage or current; an output stage drives the specified load while preserving accuracy and compliance.

• Hold and reconstruct: each code is normally held until the next update. A low-pass filter suppresses staircase images and switching energy when a smooth waveform is required.

Quantity	Symbol	Meaning
Bit depth	$n$	Number of input bits; gives $2^n$ possible codewords.
Input code	$D$	Integer represented by the applied binary word.
Reference	$V_{ref},I_{ref}$	Precision analog scale from which output weights are derived.
Zero-code output	$V_Z$	Output assigned to the minimum code before error is included.
Nominal span	$V_{FS}$	Scale used in the ideal transfer equation.
One LSB / step	$\Delta$	Ideal output increment for a one-code increase.
Update rate / period	$f_u,T_u$	New words accepted per second and their spacing; $T_u=1/f_u$.
Settling time	$t_s$	Time after an update to enter and remain in a stated final-value band.
Compliance range	—	Output-voltage interval over which a current DAC or buffer remains accurate.
Glitch impulse	$A_g$	Time integral of transient error during a code transition.

DAC quantities used throughout this section.

Ideal Transfer, Resolution and Coding

For unsigned straight-binary code

$$D=\sum_{k=0}^{n-1}b_k2^k, \qquad b_k\in\{0,1\}, \qquad 0\le D\le2^n-1,$$

a common ideal unipolar transfer is

$$\boxed{V_o(D)=V_Z+\frac{D}{2^n}V_{FS}}, \qquad \boxed{\Delta=V_{LSB}=\frac{V_{FS}}{2^n}}.$$

For $V_Z=0$ and $V_{FS}=V_{ref}$,

$$\boxed{V_o=V_{ref}\left(\frac{b_{n-1}}2+\frac{b_{n-2}}4+ \cdots+\frac{b_0}{2^n}\right)}.$$

The reference is the measuring scale, not generally the supply rail.

Ideal DAC transfer and binary weighting. An $n$-bit converter has $2^n$ output levels but only $2^n-1$ intervals between its end codes.

There are $2^n$ output levels but only $2^n-1$ transitions between end codes:

$$\begin{gathered} \boxed{\text{ideal step}=\dfrac{V_{FS}}{2^n}},\qquad \boxed{\text{maximum code}=2^n-1},\\[4pt] \boxed{\text{maximum ideal output}=V_Z+(2^n-1)\Delta}. \end{gathered}$$

Thus a unity-scaled unipolar DAC reaches $V_{ref}-1\,\mathrm{LSB}$, not $V_{ref}$. Some data sheets instead call measured endpoint-to-endpoint distance the full-scale range and divide by $2^n-1$; a numerical solution must state the convention used.

For a required nominal step no larger than $\Delta_{req}$,

$$\boxed{n_{min}=\left\lceil \log_2\!\left(\frac{V_{FS}}{\Delta_{req}}\right)\right\rceil}.$$

Each added bit doubles the levels and halves the ideal step at fixed span.

Note

Key Point — Resolution is not accuracy

Bit depth fixes the number of ideal levels and nominal step. Actual accuracy also depends on zero-code and gain error, DNL, INL, reference error, noise, settling, switching glitches, temperature and load.

Coding	Typical endpoint/zero mapping	Interpretation
Straight binary	$00\ldots0\to$ minimum; $11\ldots1\to$ maximum	All bits have positive weights; usual unipolar coding.
Offset binary	Midscale $10\ldots0\to0$	Straight binary shifted by half scale; common bipolar interface.
Two’s complement	$00\ldots0\to0$; MSB is sign	Signed integer $D_s=-b_{n-1}2^{n-1}+\sum_{k=0}^{n-2}b_k2^k$.
Thermometer	Number of ones sets level	Adjacent ideal codes switch one unit element; used internally for monotonic MSBs.
Gray code	Adjacent words differ by one bit	Reduces simultaneous input transitions but normally requires decoding.

Common DAC input-code conventions.

For an ideal bipolar two’s-complement DAC with signed integer $-2^{n-1}\le D_s\le2^{n-1}-1$ and bipolar magnitude $V_{BFS}$,

$$\boxed{V_o=\frac{D_s}{2^{n-1}}V_{BFS}}.$$

The most-negative code reaches $-V_{BFS}$, whereas the most-positive code is one LSB below $+V_{BFS}$. Offset binary gives the same ordered levels after the midscale code is subtracted.

Note

Example — Ideal DAC code and level

An ideal 8-bit unipolar DAC has $V_{ref}=5.12\,\mathrm{V}$. Its step is

$$\Delta=\frac{5.12}{256}=20\,\mathrm{mV}.$$

For $D=160=1010\,0000_2$, $V_o=160(20\,\mathrm{mV})=3.20\,\mathrm{V}$. Maximum code 255 produces $5.10\,\mathrm{V}$, one LSB below the reference.

Zero-Order Hold and Reconstruction Filtering

A clocked DAC accepts code $D[k]$ at update instants $kT_u$ and normally holds the corresponding analog level until the next update:

$$v_{ZOH}(t)=\sum_{k=-\infty}^{\infty}V_o[k] \bigl[u(t-kT_u)-u(t-(k+1)T_u)\bigr].$$

A DAC normally holds each code for one update period $T_u$. The reconstruction filter passes the wanted baseband and suppresses update images, steps and switching energy; it cannot correct static DAC nonlinearity.

The hold pulse $h_0(t)=u(t)-u(t-T_u)$ has frequency response

$$\boxed{H_{ZOH}(f)=T_u e^{-j\pi fT_u} \frac{\sin(\pi fT_u)}{\pi fT_u}}.$$

The staircase therefore has sinc amplitude droop and spectral images near integer multiples of $f_u$. A reconstruction low-pass filter passes the desired baseband and attenuates these images. For baseband bandwidth $B$, choosing $f_u>2B$ leaves a practical filter transition band; oversampling relaxes it.

Note

Key Point — What a reconstruction filter cannot fix

It can smooth update steps and reject out-of-band images, clock feedthrough and part of the glitch spectrum. It cannot recover content above Nyquist, undo clipping, or correct DAC offset, gain, DNL and INL.

Update rate, settling time and output bandwidth are different. A DAC may accept codes rapidly yet fail to settle accurately after every full-scale change. Conversely, wide small-signal bandwidth does not guarantee adequate full-scale slew rate.

Note

Example — Update rate and reconstruction margin

A waveform occupies $0$–$20\,\mathrm{kHz}$ and the DAC updates at $96\,\mathrm{kS/s}$. The Nyquist boundary is $48\,\mathrm{kHz}$, leaving $28\,\mathrm{kHz}$ for filter roll-off. ZOH magnitude at $20\,\mathrm{kHz}$ is

$$\left|\frac{\sin(\pi20/96)}{\pi20/96}\right|=0.930,$$

or about $-0.63\,\mathrm{dB}$ before inverse-sinc compensation.

Static Specifications

Let $V[D]$ be settled output and $\Delta=V_{FS}/2^n$. The actual step is

$$S_D=V[D+1]-V[D],\qquad 0\le D\le2^n-2,$$

so

$$\boxed{DNL[D]=\frac{S_D}{\Delta}-1}.$$

After the stated zero/gain treatment,

$$\boxed{INL[D]=\frac{V[D]-V_{line}[D]}{\Delta}},$$

where $V_{line}$ is an endpoint or best-fit reference line.

Representative DAC static errors. DNL measures each actual step relative to one ideal LSB; INL measures output departure from a specified straight reference line after the stated offset/gain treatment.

Specification	Definition	Consequence
Zero-code error	$V[0]-V_{ideal}[0]$	Nearly constant translation; may consume output headroom.
Offset error	Bipolar zero displacement under stated coding	Creates output at nominal zero code.
Gain error	End-scale slope error after zero removal	Error grows with code; reference calibration may reduce it.
DNL	Actual step minus one ideal LSB	Determines local step uniformity and monotonicity margin.
INL	Output departure from specified straight line	Limits absolute waveform accuracy and creates distortion.
Monotonicity	Output never reverses as code increases	Essential in control loops and programmable bias.
TUE	Worst unadjusted output error under stated conditions	Combines specified uncalibrated static terms.
Temperature drift	Error change, often ppm/$^\circ$C	Sets calibration stability over temperature.

Principal static DAC specifications.

For an increasing-output DAC,

$$\boxed{DNL[D]\ge-1\,\mathrm{LSB}\Rightarrow S_D\ge0}$$

guarantees nondecreasing output; $DNL>-1$ guarantees every step is positive. A positive DNL above $+1$ does not itself break monotonicity. A DAC cannot have an unavailable input code; the relevant failure is a zero, reverse or badly sized analog step.

Note

Example — DNL, INL and monotonicity

With ideal step $10\,\mathrm{mV}$, an actual step of $4\,\mathrm{mV}$ gives $DNL=4/10-1=-0.6\,\mathrm{LSB}$ and remains monotonic. A $-1\,\mathrm{mV}$ step gives $DNL=-1.1\,\mathrm{LSB}$ and reverses output. A corrected level error of $+18\,\mathrm{mV}$ is $+1.8\,\mathrm{LSB}$ INL.

Dynamic and Transition Specifications

DAC transition behavior. Settling time includes delay, slew and ringing; glitch impulse measures transient error area when internal switches do not change simultaneously.

Quantity	Meaning	Important distinction
Update rate $f_u$	Maximum accepted codewords per second	Does not guarantee full-scale settling at every update.
Propagation delay	Input latch to start of output response	Only one component of settling time.
Slew rate	Maximum large-signal output slope	Limits rapid large-amplitude transitions.
Settling time $t_s$	Time to enter and remain in stated band	Must name step, load and band, e.g. $\pm0.5$ LSB.
Glitch impulse $A_g$	Integrated transient error at transition	Often worst at major carry such as $0111\to1000$.
Digital feedthrough	Transient without a code change	Couples through switches, package and substrate.
Output noise density	Random output noise per $\sqrt{\mathrm{Hz}}$	Integrate over effective noise bandwidth.
SFDR	Fundamental-to-largest-spur ratio	Captures worst spur, not total noise.
THD / SINAD	Harmonic distortion / signal to noise plus distortion	Measures waveform fidelity.

Dynamic DAC specifications.

Settling contains dead time, slew-limited motion, linear settling and ringing. Crossing final value is insufficient: output must remain in the specified band. Glitch energy comes from unequal switch delay, charge injection and simultaneous bit changes. A deglitching sample-and-hold adds delay, droop and its own noise. For approximately white output-noise density $e_n$ over bandwidth $B_N$,

$$\boxed{V_{n,rms}\simeq e_n\sqrt{B_N}}.$$

Architecture Families

Principal DAC architecture families. Practical ICs often combine families, for example thermometer-coded current-source MSBs with binary LSBs.

No architecture is universally best. Selection depends on resolution, monotonicity, update and settling rate, glitch energy, output type and compliance, static power, silicon area, reference loading and calibration.

Binary-Weighted Resistor DAC

Normalized four-bit binary-weighted resistor DAC. Each switch applies $V_{ref}$ or ground; exponentially increasing branch resistances create the binary current weights.

For branch resistances $R,2R,\ldots,2^{n-1}R$ feeding an ideal virtual ground,

$$I_\Sigma=\frac{V_{ref}}{R}\left(b_{n-1}+\frac{b_{n-2}}2+ \cdots+\frac{b_0}{2^{n-1}}\right).$$

An inverting transimpedance stage gives

$$V_o=-R_fI_\Sigma.$$

Choosing $R_f=R/2$ produces the normalized law

$$\boxed{V_o=-V_{ref}\frac{D}{2^n}}.$$

The circuit is direct and fast, but an $n$-bit implementation needs resistor values spanning $R$ through $2^{n-1}R$. Ratio tolerance, switch resistance and parasitic capacitance affect branches unequally; reference current is code-dependent. This makes high-resolution matching and settling difficult.

Note

Example — Four-bit binary-weighted output

For $V_{ref}=4.096\,\mathrm{V}$, $R_f=R/2$ and code $1011_2=11$,

$$V_o=-4.096\frac{11}{16}=-2.816\,\mathrm{V}.$$

The MSB contributes $-2.048\,\mathrm{V}$ and the LSB contributes $-0.256\,\mathrm{V}$.

R–2R Ladder DAC

Four-bit R–$2R$ ladder DAC. Repeating identical sections creates binary weights while requiring only the ratio $R{:}2R$, which greatly eases matching and IC fabrication.

The termination and every repeated section present the same equivalent resistance when viewed toward the LSB end. Current arriving at each junction therefore divides by two, producing weights $1/2,1/4,\ldots,1/2^n$. With the shown current-mode polarity and transimpedance scaling,

$$\boxed{V_o=-V_{ref}\left(\frac{b_{n-1}}2+\frac{b_{n-2}}4+ \cdots+\frac{b_0}{2^n}\right)=-V_{ref}\frac{D}{2^n}}.$$

Only the ratio $R{:}2R$ must match, so process tracking is much better than for an exponential resistor set. Input resistance and switching transients are more uniform, but resistor-ratio error, switch on-resistance, op-amp settling and ladder capacitance still limit high-resolution speed. Voltage-mode ladders can reverse the orientation and buffer a Thevenin output instead of summing current.

Note

Key Point — Why R–2R is widely used

Its advantage is not that resistance is unimportant; it is that only two repeated values must maintain an accurate ratio. Absolute resistance mainly sets loading and speed, whereas ratio error sets linearity.

Resistor-String DAC

Three-bit resistor-string DAC. A decoder-controlled analog multiplexer selects one of eight ordered taps; positive resistor segments make the ideal architecture inherently monotonic.

A string of $2^n$ equal positive resistors creates ordered taps

$$\boxed{V_k=\frac{k}{2^n}V_{ref}},\qquad k=0,1,\ldots,2^n-1.$$

A binary decoder and analog multiplexer select tap $D$. Because physical tap voltages remain ordered when all segment resistances are positive, the basic architecture is inherently monotonic. DNL follows individual segment mismatch; buffer offset and switch resistance add code-dependent error.

If each segment is $R$, string current is

$$I_{string}=\frac{V_{ref}}{2^nR}.$$

Before buffering, tap resistance is approximately

$$R_{out}(D)=(DR)\parallel\bigl((2^n-D)R\bigr),$$

which is largest near midscale. The exponential number of resistors, taps, switches and decoder lines limits resolution, but monotonicity and low glitch make string DACs attractive for trimming, references and display drivers.

Capacitive Charge-Redistribution DAC

Charge-redistribution capacitor DAC. Binary capacitor ratios replace resistor ratios; CMOS implementations offer negligible static reference current but require accurate capacitor matching and careful switching.

For binary capacitors $2^{n-1}C,\ldots,C$ plus dummy $C$, total capacitance is $2^nC$. Charge conservation after bottom-plate switching gives

$$\boxed{V_o=V_{ref}\frac{D}{2^n}}$$

for the ideal polarity shown. Capacitors draw essentially no static DC reference current, integrate naturally with CMOS switches and can also sample an input, which is why charge-redistribution arrays dominate SAR ADCs.

The unsplit array area and switching energy grow exponentially with $n$. Capacitor mismatch, parasitic top-plate capacitance, switch charge injection, reference settling and $kT/C$ noise limit accuracy. Split or bridged arrays, monotonic switching sequences and calibration reduce area or switching energy.

Architecture	Main merit	Scaling cost	Dominant limits
Binary weighted $R$	Direct, simple and fast	Resistor spread $2^{n-1}{:}1$	Ratio and switch-resistance error
R–$2R$	Only $R$ and $2R$; regular layout	$O(n)$ sections	Ratio, parasitic settling, op-amp
Resistor string	Inherently monotonic, low glitch	$2^n$ segments and taps	Segment mismatch, mux, tap resistance
Capacitor array	Near-zero static current, CMOS friendly	Binary area/energy without splitting	Matching, parasitics, $kT/C$, reference settling

Comparison of passive-element DAC architectures.

Prevention: (1) place an analog anti-alias LPF before the sampler; (2) set its passband to the wanted signal and attenuate components above $f_s/2$; (3) sample above the theoretical Nyquist rate; (4) leave a guard band for filter roll-off. Once two analog frequencies produce the same sample sequence, no digital filter can separate them.

Oversampling and Undersampling

Oversampling ($f_s\gg 2f_m$) relaxes the analog filter, spreads quantization noise over a wider spectrum and enables digital decimation. Accidental undersampling violates $f_s\ge 2f_m$ and aliases destructively. Bandpass sampling can sample a narrow RF band below twice its highest carrier if a valid condition is met and a sharp preselector prevents other bands from folding in — this is not permission to violate the Nyquist condition for arbitrary baseband signals.

Telephone speech is limited to $\approx3.4\,kHz$, so $f_{\text{Nyquist}}=2(3.4)=6.8\,kHz$. Standard telephony uses $8\,kHz$, giving a $4\,kHz$ Nyquist frequency and a transition band between $3.4$ and $4\,kHz$.

Sampling Methods

Sampling waveforms: dashed input, ideal impulse samples (stems), and a flat-top (held) staircase; natural sampling would gate the input with finite-width pulses whose tops follow the signal.

Ideal / impulse sampling multiplies the signal by an impulse train $x_s(t)=x(t)\sum_n\delta(t-nT_s)$: exact values, but a mathematical model. Natural sampling gates the signal with finite-width pulses whose tops follow the input; realizable but the ADC input still changes. Flat-top sampling uses a sample-and-hold to keep one constant value over the aperture — the standard ADC waveform; finite hold width gives a sinc-shaped aperture effect. This predictable passband droop can be corrected when necessary with aperture equalization (inverse-sinc compensation) over the signal band.

Type	Pulse top	Status	Main issue
Ideal	Zero-width impulse	Model only	Not realizable
Natural	Follows input	Realizable	Input still changing
Flat-top	Constant held value	Standard ADC	Aperture / sinc droop

Comparison of the three sampling methods.

Sample-and-Hold Circuit

A sample-and-hold (S/H) circuit captures the input voltage at a selected instant and holds it nearly constant while the ADC completes conversion.

Sample-and-hold: analog switch charges hold capacitor $C_H$ during track, a high-impedance buffer isolates it during hold; the output tracks then holds each sampled value.

• Sample/track mode: switch closed, $C_H$ charges toward $v_i(t)$; output follows the input.

• Hold mode: switch open, $C_H$ retains charge; the buffer draws little charge through its high input impedance and presents low output impedance to drive the ADC, so $v_o\approx v_i(t_s)$.

Why required: an ADC takes finite time to compare and encode. If the input changes during that interval, different bit decisions correspond to different input values; holding removes this dynamic conversion error.

Specification	Meaning
Acquisition time	Time after switch closure to settle within the error band
Aperture delay	Delay from sampling command to actual disconnection
Aperture jitter	Uncertainty in the sampling instant (critical at high $f_{in}$)
Droop rate	Rate the held voltage changes due to leakage
Hold step / pedestal	Output jump from switch charge injection at hold
Feedthrough	Input/clock coupling to output during hold
Settling accuracy	Error band reached before conversion begins

Sample-and-hold specifications.

For a sinusoidal input, RMS aperture jitter $\sigma_t$ imposes the approximate SNR limit

Caution

Key Formula — Aperture-jitter SNR limit

$$\mathrm{SNR}_{\text{jitter}}\approx-20\log_{10}(2\pi f_{in}\sigma_t)\ dB.$$

Quantization

Quantization maps every held sample to the nearest member of a finite set of amplitude levels.

Uniform quantizer: staircase input-output characteristic (top) and $e_q=x-x_q$ bounded by $\pm\Delta/2$, with resets at the same thresholds (bottom).

With the convention $e_q=x-x_q$, rounding to the nearest reconstruction level gives the following ideal bounds and mean-square model.

Caution

Key Formula — Levels, resolution and error power

$$L=2^n,\qquad \Delta=\frac{V_{FS}}{2^n},\qquad -\frac{\Delta}{2}\le e_q<\frac{\Delta}{2},\qquad N_q=\sigma_q^2=\frac{\Delta^2}{12}.$$

Some data sheets use endpoint spacing $V_{FS}/(2^n-1)$; use the convention stated in the question. Modelling $e_q$ as uniform and uncorrelated gives $\sigma_q^2=\frac{1}{\Delta}\int_{-\Delta/2}^{\Delta/2}e^2\,\mathrm{d}e=\Delta^2/12$.

SQNR Derivation for a Full-Scale Sinusoid

For a bipolar range $-V_p$ to $+V_p$: $V_{FS}=2V_p$, $\Delta=2V_p/2^n$. Signal power for $x(t)=V_p\sin\omega t$ is $S=V_p^2/2$, and noise power $N_q=\frac{1}{12}(2V_p/2^n)^2$. Therefore

$$\frac{S}{N_q}=\frac{V_p^2/2}{(1/12)(2V_p/2^n)^2}=\frac{3}{2}\,2^{2n}.$$

Caution

Key Formula — Ideal full-scale-sine SQNR

$$\mathrm{SQNR}_{\mathrm{dB}}=10\log_{10}\!\frac{3}{2}+20n\log_{10}2 \approx 6.02n+1.76\ dB.$$

Every added bit ideally improves SQNR by $\approx6\,dB$. A sub-full-scale sine has the same step but less power, so its SQNR falls by the back-off in dB.

Uniform and Nonuniform Quantization

Feature	Uniform	Nonuniform
Step size	Constant	Small near zero, larger at high amplitude
Concept	Direct uniform ADC	Compressor + uniform ADC, or variable thresholds
Weak-signal SQNR	Poorer	Better
Main use	General measurement	Speech PCM

Uniform versus nonuniform quantization.

Companding

Companding combines compression at the transmitter with complementary expansion at the receiver, approximating nonuniform quantization while using a uniform quantizer internally. Speech spends much time at low amplitudes; compression enlarges the relative spacing of weak samples, reducing their fractional quantization error.

Companding chain: compressor and uniform quantizer/encoder at the transmitter; decoder and complementary expander at the receiver.

Caution

Key Formula — $\mu$-law and A-law

$$F_\mu(x)=\operatorname{sgn}(x)\frac{\ln(1+\mu\left\lvert x\right\rvert)}{\ln(1+\mu)},\qquad \mu=255.$$$$F_A(x)=\operatorname{sgn}(x) \begin{cases} \dfrac{A\left\lvert x\right\rvert}{1+\ln A}, & 0\le\left\lvert x\right\rvert<\tfrac{1}{A}, \\[6pt] \dfrac{1+\ln(A\left\lvert x\right\rvert)}{1+\ln A}, & \tfrac{1}{A}\le\left\lvert x\right\rvert\le1, \end{cases}\qquad A=87.6.$$

$\mu$-law is used in North American / Japanese PCM; A-law in European / international E1 systems. The exact SQNR benefit depends on signal level and implementation; companding redistributes quantization error but does not eliminate quantization noise.

$\mu$-law and piecewise A-law compression curves: A-law is linear for $0\le\left\lvert x\right\rvert<1/A$ and logarithmic above $1/A$; both enlarge low-level input spacing relative to the linear (dashed) response.

Feature	A-law	$\mu$-law
Parameter	$A=87.6$	$\mu=255$
Region	Europe / international	N. America / Japan
Approximation	-segment	-segment
Small-signal compression	Slightly less	Slightly greater

A-law versus $\mu$-law companding.

ADC Principle and Specifications

An ADC compares a held analog value with reference levels and encodes the result as a digital word. For an ideal unipolar converter, the nominal input range is $0\le V_{in}<V_{ref}$ and the unsigned output range is $0\le D\le 2^n-1$.

Caution

Key Formula — Ideal unipolar transfer with saturation

$$D(V_{in})= \min\!\left\{2^n-1,\, \max\!\left[0,\left\lfloor\frac{V_{in}}{V_{ref}}2^n\right\rfloor\right] \right\}.$$

Thus $V_{in}\le0$ clamps to the minimum code, while $V_{in}\ge V_{ref}$ clamps to the maximum code $2^n-1$; in particular, $V_{in}=V_{ref}$ cannot produce the nonexistent code $2^n$.

For a sinusoidal test, the standard ENOB relation is

Caution

Key Formula — Sinusoidal-test ENOB

$$\mathrm{ENOB}=\frac{\mathrm{SINAD}_{\mathrm{dB}}-1.76}{6.02}.$$

Specification	Meaning
Resolution	One LSB or $1/2^n$ of full-scale span
Conversion time	Time from conversion start to valid output
Throughput	Maximum complete conversions per second
Offset error	Horizontal shift of the transfer characteristic
Gain error	Full-scale slope error measured after offset removal
DNL / INL	Code-bin width error / deviation from ideal line
Missing code	An output code never produced
SNR / SINAD / ENOB	Noise, noise+distortion, effective resolution

Core ADC specifications.

ADC Architectures

Taxonomy of the five principal ADC architectures.

Flash ADC

An $n$-bit flash ADC uses a resistor ladder, $2^n-1$ comparators and a priority encoder: the ladder creates all thresholds, comparators compare $V_{in}$ simultaneously to give a thermometer code, and the encoder produces binary. It is the fastest type (one comparison interval) but comparator count, input capacitance, power and cost grow exponentially — an 8-bit flash needs $255$ comparators. Used in oscilloscopes, radar and direct RF/IF sampling.

Flash ADC: resistor ladder and a bank of parallel comparators feed a priority encoder.

Counter / Digital-Ramp ADC

A counter from zero drives a DAC; a comparator checks $V_{DAC}$ against $V_{in}$ and counting stops when $V_{DAC}\ge V_{in}$. Worst case needs $\approx 2^n-1$ clock periods and conversion time depends on input amplitude — simple but slow.

Counter ADC: a counter drives a DAC whose output is compared with $V_{in}$ in a feedback loop.

Successive-Approximation (SAR) ADC

A SAR ADC performs a binary search on the held input: the S/H freezes $V_{in}$; the SAR tentatively sets the MSB; the DAC converts the trial code; if $V_{DAC}\le V_{in}$ the bit is kept, else cleared; the next bit is tested down to the LSB. It takes a fixed $n$ cycles regardless of amplitude, giving a strong speed-resolution-power balance (MCUs, instrumentation).

SAR ADC: comparator, feedback DAC and successive-approximation register run an MSB-to-LSB binary search on the held input.

Dual-Slope ADC

Two integration phases: integrate unknown $V_{in}$ for a fixed $T_{int}$, then apply an opposite reference and count $T_{deint}$ to return to zero.

Caution

Key Formula — Dual-slope charge balance

$$V_{in}T_{int}=V_{ref}T_{deint}\;\Rightarrow\; V_{in}=V_{ref}\frac{T_{deint}}{T_{int}}.$$

The result depends on time and reference accuracy, not the absolute $RC$; integrating over whole mains periods gives excellent $50/60\,Hz$ rejection. Slow — widely used in digital multimeters.

Dual-slope ADC: integrator, zero comparator and control/counter integrate up on $V_{in}$ then down on $V_{ref}$.

Sigma-Delta ADC

Oversampling far above Nyquist, a feedback loop forcing average 1-bit DAC output to track the input, noise shaping that pushes quantization noise to high frequencies, and a digital decimation LPF removing out-of-band noise. Very high resolution for audio, sensors and precision measurement, with latency.

First-order sigma-delta ADC: summing node, integrator, 1-bit quantizer, 1-bit DAC feedback and a digital decimation filter.

Type	Speed	Resolution	Application
Flash	Very high	Low–med	Oscilloscope, RF DAQ
Counter	Low	Medium	Low-cost control
SAR	Med–high	Med–high	MCU, instrumentation
Dual slope	Low	High	Digital multimeter
Sigma-delta	Low BW	Very high	Audio, sensor, precision

ADC architecture comparison (speed / resolution trade-offs).

Solved Examples

Note

Example — Sampling, aliasing and prevention (5 marks)

The sampling theorem requires $f_s\ge 2f_m$ ($T_s=1/f_s$); $2f_m$ is the Nyquist rate and $f_s/2$ the Nyquist frequency. Sampling replicates $X_s(f)=\frac{1}{T_s}\sum_k X(f-kf_s)$; if $f_s<2f_m$ replicas overlap and different analog frequencies share samples — irreversible aliasing, appearing at $f_a=\left\lvert f_{in}-kf_s\right\rvert$. Sampling $f_{in}=5.5\,kHz$ at $f_s=8\,kHz$ gives $f_a=\left\lvert 5.5-8\right\rvert=2.5\,kHz$. Prevention: analog anti-alias LPF, passband $\le f_m$, attenuation above $f_s/2$, $f_s$ above Nyquist, and a guard band; oversampling relaxes the analog filter but cannot rescue already-aliased frequencies.
Practice: state both Nyquist terms, draw the replicas, compute one alias, list the prevention chain.

[!NOTE]

Example — Sampling theorem and companding (5 marks, PYQ 2082)

For $\left\lvert f\right\rvert\le f_m$, exact reconstruction needs $f_s\ge 2f_m$; if $f_s<2f_m$ replicas overlap and high frequencies fold in (aliasing, not removable digitally), so the chain is anti-alias LPF $\to$ S/H $\to$ quantizer. Companding = compression before a uniform quantizer + complementary expansion after decoding; a log compressor gives weak samples larger code spacing, improving their SQNR. Standard laws: $F_\mu(x)=\operatorname{sgn}(x)\ln(1+\mu\left\lvert x\right\rvert)/\ln(1+\mu)$ with $\mu=255$ (N. America/Japan); A-law with $A=87.6$, linear below $1/A$ and logarithmic above (Europe/E1). A $3.4\,kHz$ channel needs $\ge6.8\,kHz$ sampling; the standard $8\,kHz$ leaves a filter transition band.
Practice: reserve  2 marks for sampling/aliasing and  3 for the companding chain, both laws, constants and regional use.

[!NOTE]

Example — Quantization error and full-scale-sine SQNR (10 marks)

For an ideal $n$-bit uniform quantizer spanning $V_{FS}$: $L=2^n$, $\Delta=V_{FS}/2^n$. Nearest-level rounding bounds $-\Delta/2\le e_q<\Delta/2$; modelling $e_q$ as uniform gives $N_q=\frac{1}{\Delta}\int_{-\Delta/2}^{\Delta/2}e^2\,\mathrm{d}e=\Delta^2/12$. For a full-scale sine $x=V_p\sin\omega t$: $V_{FS}=2V_p$, $S=V_p^2/2$, $N_q=\frac{1}{12}(2V_p/2^n)^2$, so $S/N_q=\tfrac{3}{2}2^{2n}$ and $\mathrm{SQNR}_{\mathrm{dB}}=10\log_{10}(3/2)+20n\log_{10}2\approx 6.02n+1.76$. For $n=8$: $L=256$, $\mathrm{SQNR}\approx49.92\,dB$; with $V_{FS}=2\,V$, $\Delta=2/256=7.8125\,mV$ and max error $3.906\,mV$. Assumes ideal quantizer, no clipping, full-scale sine and decorrelated error.
Practice: show the error integral, substitute the bipolar step, keep power units, finish with assumptions and the 8-bit check.

[!NOTE]

Example — SAR ADC principle and operation (3+7 marks, Eng. Sewa PYQ)

Principle [3]: anti-alias LPF restricts bandwidth; the S/H samples at $f_s\ge 2f_m$ and holds; the quantizer picks one of $L=2^n$ levels ($\Delta=V_{FS}/2^n$, $\left\lvert e_q\right\rvert\le\Delta/2$); the encoder outputs $n$ bits. SAR [7]: one comparator, an $n$-bit DAC and a SAR do an MSB-to-LSB binary search — SOC freezes $V_{in}$ and clears the SAR, each bit is set, converted by the DAC, kept if $V_{DAC}\le V_{in}$ else cleared, down to the LSB, then EOC. Four-bit example, $V_{ref}=16\,V$, $V_{in}=10.4\,V$ (1 LSB $=1\,V$):

Trial	$V_{DAC}$	Decision
	8 V	keep MSB
1100	12 V	clear $b_2$
1010	10 V	keep $b_1$
1011	11 V	clear $b_0$

Result $1010_2=10$ ($10\,V$). Fixed $n$ decision clocks, unlike a counter ADC ($\approx 2^n-1$ clocks).
Practice:  5 min on the conversion chain,  12 min on the labelled loop, trial table, timing and merits.

[!NOTE]

Example — DAC transfer and resolution (5 marks)

For an ideal 8-bit DAC with $V_{ref}=5.12\,V$, one LSB is $5.12/256=20\,mV$. Code $D=160$ gives $V_o=5.12(160/256)=3.20\,V$. Binary-weighted DACs need many precise resistor values; R–2R needs only $R$ and $2R$; current steering is fastest. Nominal resolution alone is not accuracy—also check INL, DNL, gain, settling and load.
Practice: draw both resistor networks, give the ideal transfer/example, and define at least eight DAC specifications.

[!NOTE]

Key Point — Revision — A/D Conversion

• Sampling theorem $f_s\ge 2f_m$; alias $f_a=\left\lvert f_{in}-kf_s\right\rvert$; prevent with anti-alias LPF, guard band and oversampling.

• Ideal, natural, flat-top sampling differ in pulse shape; ADCs use flat-top (S/H) waveforms.

• Levels $L=2^n$, step $\Delta=V_{FS}/2^n$; rounding error $\pm\Delta/2$, power $\Delta^2/12$.

• Ideal full-scale-sine $\mathrm{SQNR}\approx 6.02n+1.76\ dB$ ($\approx6\,dB$/bit).

• Companding: $\mu$-law $\mu=255$, A-law $A=87.6$ for weak-speech SQNR.

• Flash fastest; SAR $\approx n$ cycles; dual-slope precise but slow; sigma-delta oversamples and noise-shapes.

• R–2R DAC needs only two resistor values; current steering for very high speed. Resolution $\ne$ accuracy.