Shift Registers

Register Fundamentals

A register is a group of flip-flops used to store and manipulate a binary word. An $n$-bit register contains $n$ flip-flops, normally driven by a common clock. Depending on its control circuit, data can be loaded, held, shifted, or transferred in serial or parallel form.

A shift register is a register in which the stored bits move from one flip-flop to the next on successive active clock edges.

Element	Storage capacity	Operation
Flip-flop	bit	Stores one binary state
Register	$n$ bits	Stores and transfers one binary word
Shift register	$n$ bits	Stores a word and shifts it between stages

Common register controls are:

• Clock: causes synchronous state changes.

• Enable or hold: permits a state change or retains the present word.

• Parallel load: loads all input bits on one active edge.

• Clear or reset: forces the register to a known state; it may be synchronous or asynchronous.

Four-Bit Shift-Register Principle

Let $Q_3$ be the most-significant stage and $Q_0$ the least-significant stage. A right shift moves data in the direction

$$Q_3\rightarrow Q_2\rightarrow Q_1\rightarrow Q_0.$$

For a four-stage D flip-flop register,

$$\boxed{ Q_3^+=D_{\mathrm{in}},\quad Q_2^+=Q_3,\quad Q_1^+=Q_2,\quad Q_0^+=Q_1 }.$$

Four-stage D flip-flop shift register with serial path, parallel taps, and common clock

All four flip-flops sample simultaneously. Each next state is determined by the value present at the corresponding D input immediately before the active clock edge.

Clock-by-clock state transition

For an initial state $Q_3Q_2Q_1Q_0=0000$ and serial input sequence $1,0,1,1$:

Active edge	$D_{\mathrm{in}}$	$Q_3Q_2Q_1Q_0$ after the edge
Initial	-	0000
1	1	1000
2	0	0100
3	1	1010
4	1	1101

Timing diagram for loading serial sequence 1011 into a four-bit right-shift register

SISO, SIPO, PISO and PIPO Registers

Serial and parallel input-output modes of registers

Type	Input	Output	Operation	Typical use
SISO	Serial	Serial	One bit enters and one bit leaves per clock	Serial delay and serial transfer
SIPO	Serial	Parallel	A serial word is shifted in and read simultaneously from all stages	Serial-to-parallel conversion
PISO	Parallel	Serial	A word is loaded together and shifted out one bit at a time	Parallel-to-serial conversion
PIPO	Parallel	Parallel	A complete word is loaded and read together	Temporary word storage

Serial-in serial-out register

In a SISO register, the input stream enters the first stage and passes through every stage. An $n$-stage register requires $n$ active edges to fill from an empty state. Once full, one bit enters and one bit leaves on every active edge.

Serial-in parallel-out register

A SIPO register uses the same cascaded structure but exposes all outputs $Q_{n-1},\ldots,Q_0$. After $n$ serial bits have been clocked in, the complete word is available in parallel.

Parallel-in serial-out register

A PISO register places a $2{:}1$ multiplexer before each D flip-flop. Let $L=1$ select parallel load and $L=0$ select right shift:

$$\begin{aligned} D_3 & =LP_3+\overline L D_{\mathrm{in}}, \\ D_2 & =LP_2+\overline L Q_3, \\ D_1 & =LP_1+\overline L Q_2, \\ D_0 & =LP_0+\overline L Q_1. \end{aligned}$$

Four-bit PISO register with parallel-load multiplexers and a common clock

One load edge stores $P_3P_2P_1P_0$. The loaded $Q_0$ is the first serial bit; successive shift edges expose the remaining bits at $Q_0$.

Parallel-in parallel-out register

A PIPO register loads all $n$ input bits on one active edge and presents all $n$ output bits together. With load disabled, feedback from $Q_i$ to $D_i$ holds the stored word.

Bidirectional Shift Register

A bidirectional shift register shifts either right or left. With serial inputs $SR$ and $SL$,

$$\begin{aligned} ext{right shift:}\quad (Q_3,Q_2,Q_1,Q_0)^+ & =(SR,Q_3,Q_2,Q_1), \\ ext{left shift:}\quad (Q_3,Q_2,Q_1,Q_0)^+ & =(Q_2,Q_1,Q_0,SL). \end{aligned}$$

Let $M=1$ select right shift and $M=0$ select left shift. A $2{:}1$ multiplexer before each D input gives

$$\begin{aligned} D_3 & =M(SR)+\overline M Q_2, \\ D_2 & =MQ_3+\overline M Q_1, \\ D_1 & =MQ_2+\overline M Q_0, \\ D_0 & =MQ_1+\overline M(SL). \end{aligned}$$

Universal Shift Register

A universal shift register performs hold, right shift, left shift, and parallel load. Each stage uses a $4{:}1$ multiplexer to select its next-state source.

Universal-register stage and four-bit register block

$S_1$	$S_0$	Selected source	Operation at the active edge
		Present output $Q_i$	Hold
		Right-shift source $R_i$	Shift right
		Left-shift source $L_i$	Shift left
		Parallel input $P_i$	Parallel load

The D input of stage $i$ is

$$\boxed{ D_i=\overline S_1\overline S_0Q_i +\overline S_1S_0R_i +S_1\overline S_0L_i +S_1S_0P_i }.$$

At the end stages, $R_i$ or $L_i$ is replaced by the corresponding external serial input $SR$ or $SL$.

Logical, Arithmetic and Rotate Operations

Logical right shift, arithmetic right shift, and rotate-right data paths

Operation	Next word $(Q_3,Q_2,Q_1,Q_0)^+$	Vacated position
Logical right	$(0,Q_3,Q_2,Q_1)$	Zero enters $Q_3$
Logical left	$(Q_2,Q_1,Q_0,0)$	Zero enters $Q_0$
Arithmetic right	$(Q_3,Q_3,Q_2,Q_1)$	Sign bit $Q_3$ is replicated
Arithmetic left	$(Q_2,Q_1,Q_0,0)$	Same bit movement as logical left; signed overflow may occur
Rotate right	$(Q_0,Q_3,Q_2,Q_1)$	$Q_0$ returns to $Q_3$
Rotate left	$(Q_2,Q_1,Q_0,Q_3)$	$Q_3$ returns to $Q_0$

For an unsigned word, a logical left shift multiplies by 2 modulo $2^n$, while a logical right shift gives integer division by 2. Arithmetic right shift preserves the sign of a two’s-complement number.

Timing and Performance

Setup time, hold time, and clock-to-Q delay of a register stage

• Setup time $t_{su}$: minimum interval for which input data must be stable before the active edge.

• Hold time $t_h$: minimum interval for which input data must remain stable after the active edge.

• Clock-to-output delay $t_{CQ}$: time from the active edge until the new output is valid.

For a synchronous register path,

$$\boxed{T_{clk(\min)}\ge t_{CQ(\max)}+t_{logic(\max)}+t_{su}+t_{skew}}$$

and

$$\boxed{f_{max}\le \frac{1}{T_{clk(\min)}}}.$$

All stages use the same clock, so their clock-to-Q delays do not add as $nt_{CQ}$ when determining $f_{max}$. Hold time requires a separate minimum-delay check.

For single-data-rate serial transfer, one bit is accepted per clock period:

$$\boxed{R_b=f_{clk}},\qquad \boxed{t_{n\text{-bit}}=nT_{clk}=\frac{n}{f_{clk}}}.$$

A bit captured by the first stage reaches the $n$th stage after $n-1$ further active edges. Its stage-to-stage capture latency is approximately

$$\boxed{t_{latency}=(n-1)T_{clk}+t_{CQ}}.$$

State-transition example

A four-bit register initially contains $1011$. Three right shifts apply serial inputs $0,1,0$:

Active edge	Serial input	Bit leaving $Q_0$	New state $Q_3Q_2Q_1Q_0$
Initial	-	-

Serial-loading-time example

For an 8-bit SIPO register clocked at $2\ \mathrm{MHz}$,

$$T_{clk}=\frac{1}{2\times10^6}=0.5\ \mu\mathrm{s},$$ $$\boxed{t_{load}=8T_{clk}=4\ \mu\mathrm{s}}.$$

Maximum-clock-frequency example

For $t_{CQ(\max)}=12\ \mathrm{ns}$, $t_{logic(\max)}=3\ \mathrm{ns}$, $t_{su}=5\ \mathrm{ns}$, and $t_{skew}=2\ \mathrm{ns}$,

$$T_{clk(\min)}=12+3+5+2=22\ \mathrm{ns},$$ $$\boxed{f_{max}=\frac{1}{22\ \mathrm{ns}}\approx45.5\ \mathrm{MHz}}.$$

Ring and Johnson Counters

Ring counter

A ring counter is a shift register whose last-stage output is fed directly to the first-stage input:

$$\boxed{Q_3^+=Q_0}.$$

With the one-hot initial state $1000$, a four-stage ring counter has the sequence

$$1000\rightarrow0100\rightarrow0010\rightarrow0001\rightarrow1000.$$

An $n$-stage ring counter has $n$ useful states. It must be initialized with one 1; the all-zero state is locked.

Johnson counter

A Johnson counter, or twisted-ring counter, feeds the complement of the last-stage output to the first stage:

$$\boxed{Q_3^+=\overline Q_0}.$$

Starting from $0000$, a four-stage Johnson counter has the sequence

$$\begin{aligned} 0000 & \rightarrow1000\rightarrow1100\rightarrow1110\rightarrow1111 \\ & \rightarrow0111\rightarrow0011\rightarrow0001\rightarrow0000. \end{aligned}$$

An $n$-stage Johnson counter has $2n$ useful states.

Four-bit ring and Johnson counter circuits

The state-cycle diagram makes the feedback distinction explicit: an $n$-stage ring counter has $n$ valid states, whereas a Johnson counter has $2n$.

Four-bit ring and Johnson counter state cycles

Property	Ring counter	Johnson counter
Feedback	$Q_{last}$	$\overline Q_{last}$
Useful states with $n$ flip-flops	$n$	$2n$
Normal initialization	Preset one-hot word	Clear to all zeros
State pattern	One 1 circulates	1s fill, then 0s fill
Decoding	One stage output per state	Simple two-output decoding
Main applications	One-hot timing, scanning, sequence control	Multi-phase timing, frequency division, sequence control

Standard Shift-Register ICs

IC	Width and type	Principal controls and features
	-bit SIPO	Serial input, parallel outputs, asynchronous clear
	-bit PISO	Parallel load, serial shift input, serial output
	-bit universal bidirectional	Hold, shift right, shift left, parallel load

Applications

Application	Register operation
Serial-to-parallel conversion	SIPO
Parallel-to-serial conversion	PISO
Temporary word storage and transfer	PIPO
Digital delay line	One clock-period delay per stage
Arithmetic scaling	Logical or arithmetic shift
Bit rotation	Circular feedback
One-hot timing and scanning	Ring counter
Multi-phase timing	Johnson counter
Sequence generation	Feedback shift register or counter-decoder combination