MOS Transistor Switching Characteristics

A MOSFET is a voltage-controlled, majority-carrier device. An enhancement NMOS is OFF for $V_{GS}<V_{th}$ and conducts when a positive gate overdrive $V_{OV}=V_{GS}-V_{th}$ creates an inversion channel. Its insulated gate draws negligible steady current, although gate charge must be supplied at every transition.

Drain Characteristics and Switching Regions

For an enhancement NMOS, neglecting channel-length modulation,

$$I_D=\begin{cases} 0, & V_{GS}<V_{th},\\[2pt] \mu_nC_{ox}\dfrac WL\left[(V_{GS}-V_{th})V_{DS}-\dfrac{V_{DS}^2}{2}\right], & 0\leq V_{DS}<V_{GS}-V_{th},\\[7pt] \dfrac12\mu_nC_{ox}\dfrac WL(V_{GS}-V_{th})^2, & V_{DS}\geq V_{GS}-V_{th}. \end{cases}$$

Native MOSFET drain-characteristic family and pinch-off locus; $V_{GS3}>V_{GS2}>V_{GS1}>V_{th}$.

Region	Condition	Switch interpretation
Cutoff	$V_{GS}<V_{th}$	$I_D\approx0$: open switch; $V_{DS}\approx V_{DD}$.
Triode	$V_{GS}>V_{th}$, $V_{DS}<V_{OV}$	Closed switch represented by $R_{DS(on)}$; this is the desired steady ON state.
Saturation	$V_{GS}>V_{th}$, $V_{DS}\geq V_{OV}$	Current-source region, crossed during hard switching and used for amplification.

For small $V_{DS}$,

Caution

Key Formula — ON resistance and conduction loss

$$R_{DS(on)}\approx \frac{1}{\mu_nC_{ox}(W/L)(V_{GS}-V_{th})},\qquad P_{cond}=I_{D,\mathrm{rms}}^2R_{DS(on)}.$$

Greater gate overdrive and larger $W/L$ reduce resistance. Practical $R_{DS(on)}$ rises with junction temperature.

Resistive-Load Switching Path

MOSFET switch and its DC load-line endpoints.

Dynamic Switching and the Miller Plateau

The gate driver charges $C_{GS}$ and $C_{GD}$; the data-sheet input capacitance is $C_{iss}=C_{GS}+C_{GD}$. Turn-on occurs in three useful stages:

1. $V_{GS}$ rises to $V_{th}$ while $I_D\approx0$ (delay time).

2. $I_D$ rises to the load current; $V_{GS}$ reaches the plateau level.

3. Gate-drain charge $Q_{GD}$ is supplied while $V_{DS}$ falls. This nearly flat part of $V_{GS}$ is the Miller plateau; afterward the gate rises to its final drive voltage.

Turn-off is the reverse sequence. A useful charge-based estimate is $t\approx Q_g/I_g$; the simpler RC estimate is $t_r\approx2.2R_gC_{iss}$.

Idealized gate-voltage and drain-voltage turn-on waveforms.

Caution

Key Formula — MOSFET switching losses

For a hard-switched device at switching frequency $f_s$,

$$P_{sw}\approx\frac12V_{DD}I_D(t_r+t_f)f_s, \qquad P_g\approx Q_gV_{GS}f_s.$$

For a capacitive load, $P_{dyn}=C_LV_{DD}^2f_s$. Device selection must compare all losses at the actual current, frequency and temperature.

BJT–MOSFET Switching Comparison

Feature	BJT	MOSFET
Control	Base-current controlled	Gate-voltage controlled
Carriers	Bipolar; minority charge stored	Unipolar; no minority storage
Steady ON state	Saturation, $V_{CE(sat)}$	Deep triode, $R_{DS(on)}$
Dominant delay	Storage time $t_s$	Gate charge, especially $Q_{GD}$
Drive power	Continuous $V_{BE}I_B$	Dynamic $Q_gV_{GS}f_s$
Conduction loss	$V_{CE(sat)}I_C$	$I_{D,\mathrm{rms}}^2R_{DS(on)}$
Temperature sharing	Thermal-runaway prone	Positive $R_{DS(on)}$ coefficient aids sharing
Typical strength	Gain and low fixed ON drop	Fast switching and high integration density

Integrated MOSFET Fundamentals and Practical Effects

The switching model is extended here with MOS construction, device types, symbols, static characteristics, circuit operation, second-order effects and a consolidated comparison matrix.

Device Idea, Terminals and Classification

A MOSFET is a voltage-controlled, majority-carrier semiconductor device in which an electric field produced by the insulated gate controls the conductivity of a channel between source and drain. Ideally the gate draws no steady DC current; practical gate current is required only to charge and discharge capacitances during transitions.

A MOSFET has four physical terminals:

• Gate (G): the control electrode, insulated by a thin oxide.

• Source (S): the terminal from which the channel’s majority carriers enter.

• Drain (D): the terminal through which those carriers leave.

• Body or bulk (B): the semiconductor substrate. In most discrete three-terminal MOSFETs the body is internally connected to source.

Classification of MOSFETs by channel polarity and operating mode.

Note

Key Point — Why MOSFETs Have Very High Input Resistance

The gate and semiconductor are separated by silicon dioxide, so there is no forward-biased gate junction in normal operation. The input therefore behaves mainly as a capacitor. DC input resistance is extremely high, but a switching driver must still supply the finite gate charge $Q_g$.

Essential Notation

Symbol	Meaning	Symbol	Meaning
$V_{GS}$	Gate-to-source voltage	$V_{DS}$	Drain-to-source voltage
$I_D$	Conventional drain current	$V_{th}$	Threshold voltage
$V_{OV}$	Overdrive, $V_{GS}-V_{th}$	$C_{ox}$	Oxide capacitance per unit area
$W/L$	Channel width-to-length ratio	$\lambda$	Channel-length-modulation parameter
$I_{DSS}$	Depletion-device current at $V_{GS}=0$	$V_{GS(off)}$	Gate voltage that cuts off a depletion device

Construction and Channel Formation

Enhancement NMOS and PMOS Structures

Cross-sections after a sufficient gate voltage has induced a channel. No conducting channel exists at $V_{GS}=0$ in an enhancement MOSFET.

Formation of the NMOS Inversion Layer

Consider a positive drain voltage and increase $V_{GS}$ from zero:

1. Accumulation is absent: at $V_{GS}=0$, the two $n^+$ regions form reverse-biased junctions with the P-body, so source and drain remain isolated.

2. Depletion: a small positive gate voltage repels holes from the surface, leaving fixed negatively charged acceptor ions.

3. Inversion: a larger positive voltage attracts electrons to the oxide interface. At $V_{GS}=V_{th}$ the surface changes effectively from P-type to N-type.

4. Conduction: for $V_{GS}>V_{th}$ the inversion layer joins source and drain. A positive $V_{DS}$ drives electron flow from source to drain, while conventional $I_D$ flows from drain to source.

For PMOS every semiconductor type and voltage polarity is reversed: an N-body contains $p^+$ source/drain regions, a sufficiently negative $V_{GS}$ creates a hole channel, and conventional current normally flows from source to drain. It is often clearer to use positive magnitudes $V_{SG}$ and $V_{SD}$ for PMOS analysis.

Caution

Key Formula — Threshold and Geometry Parameters

The oxide capacitance and device transconductance parameter are

$$C_{ox}=\frac{\epsilon_{ox}}{t_{ox}},\qquad \beta_n=\mu_n C_{ox}\frac{W}{L}.$$

A thinner oxide, larger mobility, or larger $W/L$ gives more drain current for the same overdrive. Process texts sometimes call $\mu_nC_{ox}$ by $k_n'$ and $\mu_nC_{ox}(W/L)$ by $k_n$ or $\beta_n$; always inspect the definition before using a factor of $1/2$.

Enhancement and Depletion MOSFETs

Proper Schematic Symbols

Standard insulated-gate FET symbols drawn with CircuitikZ. A broken channel denotes enhancement mode; a solid channel denotes depletion mode.

Note

Key Point — Reading the Symbols Correctly

• Broken channel: no channel at zero gate bias, so the device is normally OFF.

• Solid channel: a fabricated channel exists, so the device is normally ON.

• The body arrow follows the P-to-N junction convention. Symbol variants can place the arrow differently, so identify channel type from the complete symbol and terminal labels rather than relying only on a mnemonic.

Depletion-Mode Operation

A depletion MOSFET is fabricated with a physical channel joining source and drain. Consequently it conducts at $V_{GS}=0$.

For an N-channel depletion MOSFET:

• $V_{GS}<0$ repels electrons and narrows the channel (depletion operation). At $V_{GS}=V_{GS(off)}<0$, the channel is cut off.

• $V_{GS}>0$ attracts additional electrons and raises the current above $I_{DSS}$ (enhancement operation).

The P-channel device has all polarities reversed.

Caution

Key Formula — Shockley Transfer Relation for a Depletion MOSFET

In the saturation region, the commonly used square-law model is

$$I_D=I_{DSS}\left(1-\frac{V_{GS}}{V_{GS(off)}}\right)^2.$$

For an N-channel device, $V_{GS(off)}$ is negative. Thus $I_D=I_{DSS}$ at $V_{GS}=0$ and $I_D=0$ at $V_{GS}=V_{GS(off)}$. Some books denote $|V_{GS(off)}|$ by $V_P$; substituting signs carelessly produces an incorrect transfer characteristic.

Enhancement NMOS Operating Regions

Assume a long-channel enhancement NMOS with body tied to source and define

$$V_{OV}=V_{GS}-V_{th},\qquad \beta_n=\mu_nC_{ox}\frac WL.$$

Region	Condition	Drain current and meaning
Cutoff	$V_{GS}<V_{th}$	$I_D\approx0$. No strong inversion channel; the device acts as an open switch.
Triode, linear or ohmic	$V_{GS}\geq V_{th}$ and $0\leq V_{DS}<V_{OV}$	$I_D=\beta_n\left(V_{OV}V_{DS}-V_{DS}^2/2\right)$. The channel exists from source to drain and behaves as a voltage-controlled resistance.
Saturation or active	$V_{GS}\geq V_{th}$ and $V_{DS}\geq V_{OV}$	$I_D=(\beta_n/2)V_{OV}^2$ ideally. The channel pinches off near the drain; current is mainly controlled by $V_{GS}$.

Conceptual channel shape in the three NMOS operating regions. In saturation the inversion channel ends before the drain, but the strong electric field carries electrons across the short pinch-off region.

What Pinch-Off Actually Means

The channel voltage is not constant from source to drain. Let $V(x)$ be the local channel potential measured from the source. The NMOS inversion charge per unit area is approximately

$$Q_i(x)=-C_{ox}\bigl[V_{GS}-V_{th}-V(x)\bigr].$$

It is largest near the source, where $V(x)\approx0$, and becomes smaller toward the drain as $V(x)$ rises. At the drain end, $V(L)=V_{DS}$, so

$$Q_i(L)=-C_{ox}\bigl[V_{GS}-V_{th}-V_{DS}\bigr] =-C_{ox}(V_{OV}-V_{DS}).$$

• Before pinch-off: When $V_{DS}<V_{OV}$, the bracket remains positive even at the drain. A continuous inversion channel reaches from source to drain, so the MOSFET is in triode.

• Pinch-off boundary: At $V_{DS}=V_{OV}=V_{GS}-V_{th}$, the inversion charge at the drain end becomes zero. In the ideal model the channel tapers to zero at the drain edge; this marks the beginning of saturation.

• Current does not stop: Electrons travel through the inversion channel to the pinch-off point and are then swept rapidly across the short drain depletion region by its strong electric field. Pinch-off therefore does not mean an open circuit.

• Beyond pinch-off: Extra $V_{DS}$ falls mainly across the pinch-off region rather than increasing channel charge. The ideal long-channel current is therefore nearly constant at $I_D=(\beta_n/2)V_{OV}^{2}$.

At $V_{DS}=V_{OV}$, the triode equation gives the same current as the saturation equation, so the mathematical model is continuous. In a real device, increasing $V_{DS}$ moves the pinch-off point slightly toward the source and shortens the effective channel. This channel-length modulation causes the small upward slope of the saturation curves.

Note

Key Point — Pinch-Off Is Not Cutoff

Drain-end pinch-off occurs with the MOSFET ON and marks saturation; $I_D$ continues to flow. Cutoff occurs when the gate does not create or sustain a channel and $I_D\approx0$. For a depletion MOSFET, some texts call $V_{GS(off)}$ the pinch-off voltage; that gate-controlled channel cutoff is different from drain-end pinch-off at the onset of saturation.

[!IMPORTANT]

Key Formula — Practical Saturation Model and Small-Signal Parameters

Channel-length modulation gives a slight upward slope in saturation:

$$I_D\approx\frac12\beta_nV_{OV}^2(1+\lambda V_{DS}),\qquad g_m=\frac{\partial I_D}{\partial V_{GS}} =\beta_nV_{OV}=\frac{2I_D}{V_{OV}},\qquad r_o\approx\frac{1}{\lambda I_D}.$$

The intrinsic voltage gain of a common-source stage is roughly $g_mr_o$.

PMOS Region Test

Use magnitudes to avoid sign mistakes. For a PMOS define $V_{SG}=V_S-V_G$, $V_{SD}=V_S-V_D$, and $|V_{tp}|$. Then it is:

• ON when $V_{SG}\geq|V_{tp}|$;

• in triode when $V_{SD}<V_{SG}-|V_{tp}|$;

• in saturation when $V_{SD}\geq V_{SG}-|V_{tp}|$.

The current magnitude follows the same square-law equations with $\beta_p$. PMOS drain-end pinch-off begins at $V_{SD}=V_{SG}-|V_{tp}|$; holes continue across the high-field region just as electrons do in NMOS, with all polarities and carrier directions reversed.

Static Characteristics

Drain Characteristics: $I_D$ versus $V_{DS}$

Enhancement-NMOS output characteristics. The small positive slope in saturation represents channel-length modulation; $V_{GS3}>V_{GS2}>V_{GS1}$.

At low $V_{DS}$ the device is approximately resistive:

Caution

Key Formula — Approximate ON Resistance

$$R_{DS(on)}\approx \frac{1}{\mu_nC_{ox}(W/L)(V_{GS}-V_{th})},\qquad P_{cond}=I_{D,\mathrm{rms}}^2R_{DS(on)}.$$

This first-order expression omits source/drain and package resistance. Data-sheet $R_{DS(on)}$ is the value to use for a power MOSFET, and it must be corrected for gate voltage and junction temperature.

Transfer Characteristics: $I_D$ versus $V_{GS}$

Conceptual transfer characteristics of all four MOSFET types. Current magnitudes are shown for P-channel devices.

MOSFET Circuits

Low-Side NMOS and High-Side PMOS Switches

Low-side NMOS switch (left) and high-side PMOS switch (right). $D$, $S$, and $G$ identify drain, source, and gate; the red arrow shows conventional current when the switch is ON. $R_{pd}$ and $R_{pu}$ define a safe OFF state when the controller output is floating; $R_g$ limits peak gate current and controls ringing. A HIGH gate drive turns the NMOS ON; a LOW control voltage turns the PMOS ON.

Note

Key Point — Why This Pairing Is Common

• Low-side NMOS: The MOSFET lies between the load and ground. Its source is fixed at ground, so an ordinary ground-referenced controller can make $V_{GS}$ positive simply by driving the gate HIGH.

• High-side PMOS: The MOSFET lies between $V_{DD}$ and the load. Its source is fixed at $V_{DD}$; driving the gate up to $V_{DD}$ turns it OFF, while pulling the gate LOW makes $V_{GS}<0$ and turns it ON. No gate voltage above $V_{DD}$ is needed.

• It is a convenient pairing, not a law: A high-side NMOS is common in efficient power circuits, but its driver must raise the gate above its source, usually with a bootstrap circuit or charge pump.

[!NOTE]

Key Point — Which Terminal Is Source and Which Is Drain?

In Figure 1.7, the NMOS source $S$ is the lower terminal connected to ground and its drain $D$ faces the load. For the PMOS, the source $S$ is the upper terminal connected to $V_{DD}$ and its drain $D$ faces the load. Thus normal conventional current flows $D\to S$ through the NMOS, but $S\to D$ through the PMOS.

For the low-side NMOS switch:

• NMOS OFF: $V_{GS}<V_{th}$, $I_D\approx 0$, and $V_{DS}\approx V_{DD}$.

• NMOS ON: The driver must provide the data-sheet test gate voltage, not merely exceed $V_{th}$. The device operates in deep triode and $V_{DS(on)}\approx I_DR_{DS(on)}$.

Note

Law — Threshold Voltage Is Not the Full-ON Voltage

Data-sheet $V_{GS(th)}$ is measured at a very small drain current. It only says when a weak channel begins to form. A switch must be driven at a gate voltage for which $R_{DS(on)}$ is specified; otherwise conduction loss and heating can be much larger than expected.

Voltage-Divider-Biased Common-Source Amplifier

Common-source amplifier with divider bias, source stabilization and an optional AC bypass capacitor $C_S$.

For negligible gate current,

$$V_G\approx V_{DD}\frac{R_2}{R_1+R_2},\quad V_S=I_DR_S,\quad V_{GS}=V_G-V_S,\quad V_{DS}=V_{DD}-I_D(R_D+R_S).$$

The bias point must satisfy the saturation test $V_{DS}\geq V_{GS}-V_{th}$. With $C_S$ effective at signal frequency, the approximate midband gain is $A_v\approx-g_m(R_D\parallel r_o\parallel R_L)$; without bypassing, source degeneration lowers gain but improves linearity and bias stability.

Dynamic Switching and Gate Charge

The insulated gate is not an open circuit during switching. Important capacitances are $C_{GS}$, $C_{GD}$ and $C_{DS}$, with $C_{iss}=C_{GS}+C_{GD}$. The gate-drain capacitance causes the Miller plateau while the drain voltage changes.

Idealized hard-switching turn-on sequence. $I_D$ rises before $V_{DS}$ falls; their overlap produces switching loss.

1. The driver charges the gate to $V_{th}$; drain current is still nearly zero.

2. Drain current rises to the load current as $V_{GS}$ approaches the plateau voltage.

3. Gate-drain charge $Q_{GD}$ is supplied while $V_{DS}$ falls. Gate voltage remains nearly constant at the Miller plateau.

4. After the plateau, the gate reaches its final drive voltage and $R_{DS(on)}$ reaches its specified low value.

Caution

Key Formula — First-Order Switching Estimates

$$t_{sw}\approx\frac{Q}{I_g},\qquad P_{sw}\approx\frac12V_{DS}I_D(t_r+t_f)f_s, \qquad P_g=Q_gV_{drive}f_s.$$

$P_{sw}$ estimates drain switching loss for approximately linear voltage and current transitions. $P_g$ is the power that the gate driver must supply; it is not dissipated entirely inside the MOSFET.

Second-Order Effects and Practical Limits

Effect	Physical result	Practical consequence
Channel-length modulation	Pinch-off point moves toward source as $V_{DS}$ increases	Saturation curves slope upward; finite $r_o$ lowers amplifier gain.
Body effect	Source-body reverse bias raises NMOS threshold	Use $V_{th}=V_{th0}+\gamma(\sqrt{2\phi_F+V_{SB}}-\sqrt{2\phi_F})$.
Subthreshold conduction	Weak inversion current remains below threshold	Cutoff current is not exactly zero; leakage matters in low-power ICs.
Body diode	Body-source connection forms an intrinsic diode	It conducts reverse current in power circuits and has reverse-recovery implications.
Temperature rise	Mobility falls and power-device $R_{DS(on)}$ usually rises	Use hot $R_{DS(on)}$, thermal resistance and safe operating area.
Avalanche and oxide stress	Excess $V_{DS}$ avalanches the drain junction; excess $V_{GS}$ damages oxide	Never exceed absolute maximum ratings; clamp inductive transients and gate spikes.

Summary and Comparison Matrix

Property	N-enhancement	P-enhancement	N-depletion	P-depletion
At $V_{GS}=0$	OFF; no channel	OFF; no channel	ON; channel exists	ON; channel exists
Major carriers	Electrons	Holes	Electrons	Holes
Gate action	Positive $V_{GS}$ turns ON	Negative $V_{GS}$ turns ON	Negative depletes; positive enhances	Positive depletes; negative enhances
Cutoff voltage	$V_{GS}<+V_{th}$	$V_{SG}<	V_{tp}	$
Symbol channel	Broken	Broken	Solid	Solid
Usual current direction	D to S	S to D	D to S	S to D
Typical use	Low-side switch, CMOS pull-down	High-side switch, CMOS pull-up	Current source, special analog circuits	Less common complementary analog use

MOSFET versus BJT

Feature	MOSFET	BJT
Control variable	Gate voltage and gate charge	Base current
Carrier mechanism	Majority-carrier, unipolar	Both carrier types, bipolar
Input resistance	Extremely high at DC	Finite because base-emitter junction conducts
Steady ON model	$R_{DS(on)}$ in deep triode	$V_{CE(sat)}$ in saturation
Dynamic limitation	Gate and Miller charge	Stored minority charge and base charge
Conduction loss	$I_{D,\mathrm{rms}}^2R_{DS(on)}$	Approximately $V_{CE(sat)}I_C$
Thermal sharing	Positive $R_{DS(on)}$ coefficient often helps	Thermal runaway is more problematic