A/D Converters

An analog-to-digital converter (ADC) samples a continuous input, assigns each sample to one of a finite number of amplitude levels (quantization), and encodes that level as a binary word. A complete data-acquisition path therefore uses anti-alias filtering, sampling/holding, quantization and encoding.

ADC Language, Conversion Chain and Ideal Transfer

A complete ADC signal path: sampling discretizes time, quantization discretizes amplitude, and encoding expresses the selected level in binary.

The three conversion operations are distinct:

• Sampling: selects values at $t=kT_s$ and therefore discretizes time; $T_s=1/f_s$.

• Quantization: maps each held value to one of $2^n$ amplitude intervals and is the irreversible step.

• Encoding: labels the selected interval with an $n$-bit binary word; it introduces no additional ideal error.

Fundamental quantities and vocabulary

Quantity	Symbol	Definition
Analog input	$v_i(t)$	Continuous-time voltage presented to the ADC front end.
Sample	$v_i[k]=v_i(kT_s)$	Input value selected at sampling instant $kT_s$.
Sampling rate/period	$f_s,\ T_s$	Samples requested per second and their spacing; $T_s=1/f_s$.
Bit depth	$n$	Number of binary digits in one output codeword.
Number of codes	$L=2^n$	Distinct digital words, numbered $0$ through $2^n-1$.
Input limits	$V_{min},V_{max}$	Lowest and highest specified analog inputs.
Full-scale span	$V_{FS}$	Width of the input range: $V_{FS}=V_{max}-V_{min}$.
Reference	$V_{ref}$	Precision voltage that establishes the converter scale; for a simple unipolar ADC, $V_{ref}=V_{FS}$.
Step size / 1 LSB	$\Delta,V_{LSB}$	Ideal width of one code bin in volts: $\Delta=V_{FS}/2^n$.
Code / codeword	$D$	Integer bin index and its $n$-bit representation.
Transition voltage	$V_k$	Input boundary at which the output changes from code $k-1$ to $k$.
Code bin	—	Input interval producing one code; ideal width is $\Delta$.
Quantized estimate	$\hat v_i$	Analog value assigned to the selected code, often its bin midpoint.
Quantization error	$q_e$	Difference $v_i-\hat v_i$ caused by finite amplitude bins.
Clipping / overrange	—	Input lies outside the allowed span, so the output remains at an end code.

ADC quantities used throughout this chapter.

Resolution in detail

The bit depth $n$ fixes the number of available codewords, $2^n$. The word resolution may mean bit depth, one ideal LSB in volts, or the fractional step $1/2^n$ of full-scale span. It describes granularity, not total measurement accuracy.

Thus resolution may be reported in three equivalent ideal forms:

$$\boxed{n\ \text{bits}},\qquad \boxed{\Delta=\frac{V_{FS}}{2^n}\ \text{volts/code}},\qquad \boxed{\frac{100}{2^n}\%\ \text{of span per code}}.$$

Let $V_{FS}=V_{max}-V_{min}$ be the allowed input span. For an ideal $n$-bit uniform ADC,

$$\boxed{L=2^n\ \text{codes}},\qquad \boxed{\Delta=V_{LSB}=\frac{V_{FS}}{2^n}},$$ $$\boxed{D=\operatorname{clip}_{0}^{2^n-1} \left(\left\lfloor\frac{v_i-V_{min}}{\Delta}\right\rfloor\right)}.$$

The nominal, non-overload range is the half-open interval $V_{min}\le v_i<V_{max}$; values outside it, including $v_i\ge V_{max}$, saturate at an end code. If code $D$ represents the midpoint of its interval, then, within the nominal range,

$$\hat v_i=V_{min}+\left(D+\frac12\right)\Delta, \qquad \boxed{q_e=v_i-\hat v_i\in \left[-\frac{\Delta}{2},\frac{\Delta}{2}\right)}, \qquad \sigma_q^2\simeq\frac{\Delta^2}{12}.$$

The variance model assumes no overload and quantization error that is approximately uniform and uncorrelated with the input, as occurs for a sufficiently active or dithered signal. For DC or coherent low-level inputs, the error can instead be deterministic and correlated. Bipolar and offset-binary converters use the same span rule with a shifted code origin. Datasheets occasionally quote endpoint spacing $V_{FS}/(2^n-1)$, so the convention stated in a numerical problem must be followed.

Resolution answers the ideal question, “how finely is the selected input span divided?” It depends on both bit depth and span:

• increasing $n$ by one doubles the number of codes and halves $\Delta$;

• keeping $n$ fixed but narrowing $V_{FS}$ also reduces $\Delta$, although it reduces allowable input headroom and may cause clipping;

• widening a bipolar range means using its complete span. For example, a $\pm5\,\mathrm{V}$ range has $V_{FS}=10\,\mathrm{V}$, not $5\,\mathrm{V}$.

For a required ideal voltage increment $\Delta_{req}$, the minimum bit depth is

$$\boxed{n_{min}=\left\lceil \log_2\!\left(\frac{V_{FS}}{\Delta_{req}}\right) \right\rceil}.$$

This calculation selects nominal granularity only. Noise, DNL, INL, offset, gain and reference uncertainty determine whether such a small input change can actually be distinguished or measured accurately.

Term	Meaning
Nominal resolution	Ideal code count or code-bin width: $2^n$ codes and $\Delta=V_{FS}/2^n$.
Accuracy	Closeness of the reported value to the true input after systematic and random errors.
Effective resolution/ENOB	Usable dynamic resolution inferred from measured noise plus distortion, generally less than $n$.
Noise-free resolution	Stable code divisions remaining after peak-to-peak code flicker or transition noise.
Sensitivity	Smallest input change producing a reliably observable output change under stated test conditions.

Meanings that must not be confused with nominal resolution.

Note

Example — Selecting resolution from span

A $0$–$5\,\mathrm{V}$ ADC must have an ideal step no greater than $1\,\mathrm{mV}$. Since

$$n_{min}=\left\lceil\log_2\!\left(\frac{5}{0.001}\right)\right\rceil =\lceil12.29\rceil=13,$$

a $13$-bit converter is required by ideal granularity. Its step is $5/8192=610.4\,\mathrm{\mu V}$. A $12$-bit converter gives $1.221\,\mathrm{mV}$ and does not meet the requirement, even before practical errors are included.

Reference voltage in detail

The reference voltage is the precision analog standard against which the sampled input is compared. It establishes the converter’s transfer scale: its value determines the ideal transition voltages and therefore the number of input volts represented by one code.

The reference is the ADC’s measuring ruler; it is not simply the supply voltage. The analog supply powers the circuitry, whereas the reference defines the scale. Some ADCs contain a factory-trimmed internal reference, some require an external reference, and others permit either. In every case the input, reference and supply pins must obey the ranges stated in the datasheet.

For a common unity-scaled unipolar ADC with $V_{min}=0$,

$$V_{FS}=V_{ref},\qquad \Delta=\frac{V_{ref}}{2^n},\qquad V_k=k\Delta\quad(k=1,2,\ldots,2^n-1).$$

More generally, a converter may use positive and negative reference pins, internal scaling or bipolar input translation. A useful model is

$$\boxed{V_{FS}=G_{ref} \left(V_{\mathrm{REF}+}-V_{\mathrm{REF}-}\right)},\qquad \boxed{\Delta=\frac{G_{ref} \left(V_{\mathrm{REF}+}-V_{\mathrm{REF}-}\right)}{2^n}},$$

where its datasheet defines $G_{ref}$. Therefore $V_{ref}=V_{FS}$ only in the simple unity-scaled case.

Changing the reference does not create more digital codes: an $n$-bit ADC still has $2^n$ codewords. A lower permitted reference reduces volts per code but also reduces input headroom, and makes fixed input noise and offset larger when expressed in LSBs. In the simple unipolar model the last code covers $[V_{ref}-\Delta,V_{ref})$; $V_{ref}$ is the upper range boundary, not an additional code value.

Away from clipping, the ideal code is proportional to $V_{in}/V_{ref}$. Thus a small reference change has opposite signs depending on what is held fixed:

$$\boxed{\left.\frac{\delta D}{D}\right|_{V_{in}} \simeq-\frac{\delta V_{ref}}{V_{ref}}},\qquad \boxed{\left.\frac{\delta\hat v_i}{\hat v_i}\right|_D \simeq+\frac{\delta V_{ref}}{V_{ref}}}.$$

A higher actual reference therefore produces fewer codes for the same input, while a fixed code represents more volts.

Reference property	Effect on conversion
Initial accuracy	A constant reference-ratio error produces a full-scale or gain error.
Temperature coefficient	Drift in $\mathrm{ppm}/{}^\circ\mathrm{C}$ causes the transfer scale to move with temperature.
Noise	Moving thresholds cause code flicker and reduce SNR, SINAD and ENOB.
Output impedance	Dynamic ADC reference current can disturb the voltage at the reference pin.
Settling/load recovery	Incomplete recovery can create signal- and code-dependent conversion error.
Long-term drift	Calibrated gain changes over months or years.
Bypass network	Local charge storage supports transients; poor placement or unsuitable capacitance increases error.

Reference properties and their ADC consequences.

An internal reference simplifies design, while an external one can offer a different range, noise or drift grade. Either must satisfy the specified drive and decoupling requirements. A ratiometric system excites a sensor and references the ADC from the same source. If $V_{in}=\alpha V_{ref}$, then

$$D\approx\left\lfloor\alpha2^n\right\rfloor,$$

so common slow reference changes cancel from the ideal code ratio. This does not cancel reference noise, settling error, offset or nonlinearity.

Note

Example — Reference voltage sets volts per code

For a unity-scaled $12$-bit ADC with $V_{ref}=4.096\,\mathrm{V}$,

$$\Delta=\frac{4.096}{4096}=1.000\,\mathrm{mV/code}.$$

If the actual reference is $0.1\%$ high, it is $4.100096\,\mathrm{V}$ and the actual step is $1.001\,\mathrm{mV/code}$. Bit depth is still $12$: volts per code is $0.1\%$ high, while code-per-volt gain is about $0.1\%$ low. Near full scale the transition displacement is approximately $4.096\,\mathrm{mV}$, or $4.096$ nominal LSBs, before calibration.

Ideal uniform ADC model. Each horizontal code bin has width $\Delta$; midpoint reconstruction produces a bounded sawtooth error over the nominal half-open range. The point at $V_{max}$ is clipped to the top code.

Common output coding conventions

Coding	Typical range and zero code	Interpretation
Straight binary	Unipolar; $00\ldots0$ is the minimum input	All bits have positive weights.
Offset binary	Bipolar; midscale $10\ldots0$ represents zero	Straight binary shifted by half scale.
Two’s complement	Bipolar; $00\ldots0$ represents zero	MSB has negative sign weight; convenient for arithmetic.
Gray or thermometer code	Internal high-speed stages	Adjacent states change minimally; translated before normal binary output.

Common ADC code conventions.

Note

Key Point — Code value versus represented voltage

The integer code $D$ names an interval, not an exact analog voltage. A question must state whether the reported analog estimate is the lower edge, midpoint, or another calibrated value. Keep that convention consistent when quoting error.

Sampling, Anti-Aliasing and Sample-and-Hold

The sampling rate $f_s$ is the number of sampling instants per second; the sampling period is $T_s=1/f_s$. The signal bandwidth $B$ is the highest baseband frequency that must be preserved. The Nyquist rate is $2B$, whereas the Nyquist frequency for an already chosen $f_s$ is $f_s/2$.

An ideally band-limited baseband input can be reconstructed if

$$\boxed{f_s\ge2B}.$$

Sampling replicates the analog spectrum around integer multiples of $f_s$. Aliasing occurs when these replicas overlap, making different analog frequencies produce the same samples. A sinusoid at $f_{in}$ appears in the first Nyquist zone at

$$\boxed{f_a=\left|f_{in}-kf_s\right|},\qquad 0\le f_a\le\frac{f_s}{2},$$

where integer $k$ is chosen to place $f_a$ in that interval. Because aliasing is irreversible after sampling, a realizable analog anti-alias low-pass filter and a guard band require $f_s>2B$ in practice.

Sampling rate in detail

Sampling rate determines how closely samples are spaced in time; it does not determine amplitude resolution. At $f_s$ samples per second, adjacent ideal aperture instants are $T_s=1/f_s$ apart. A sinusoid at $f_{in}$ is represented by

$$\boxed{N_{samples/cycle}=\frac{f_s}{f_{in}}}$$

samples per cycle. Increasing this ratio gives a denser time record and can ease waveform processing, but it neither adds nominal ADC bits nor removes analog errors by itself.

The Nyquist inequality is a mathematical lower bound for an ideally band-limited signal, not a complete hardware design rule. Equality $f_s=2B$ leaves no transition band for a realizable anti-alias filter and can sample a band-edge tone at an unfortunate phase. In practice one chooses $f_s>2B$, passes the wanted band to $B$, and attenuates unwanted analog content before it can fold into that band. The oversampling ratio is

$$\boxed{OSR=\frac{f_s}{2B}}.$$

An $OSR>1$ provides filter guard band. With suitable digital low-pass filtering and decimation, oversampling can also reduce in-band white noise. Merely collecting more noisy samples without filtering does not guarantee higher accuracy.

Quantity	Meaning
Sampling rate $f_s$	Aperture instants per second; it sets $T_s$ and the Nyquist frequency $f_s/2$.
Throughput/output rate	Completed codewords delivered per second; it may differ from sampling rate.
Conversion clock	Clock used for internal bit decisions; several cycles may be required per sample.
Conversion time	Time the architecture needs to determine one sampled code.
Latency	Delay from one sample’s aperture instant until that sample’s code appears.
Analog input bandwidth	Front-end frequency range that can reach the sampler, not the unaliased baseband limit.
Per-channel sample rate	Rate seen by one channel; in an $M$-channel scan it is at most roughly aggregate rate/$M$.

Rates and bandwidths often confused in ADC specifications.

Architecture and acquisition impose an additional upper limit. A basic SAR conversion cycle must provide time to acquire and convert,

$$\boxed{T_s\ge t_{acq}+t_{conv}+t_{overhead}},\qquad f_s\le\frac{1}{t_{acq}+t_{conv}+t_{overhead}}.$$

A pipeline ADC can deliver one result each clock after a multi-cycle latency; a sigma-delta modulator samples internally much faster than its decimated output-word rate. After a multiplexer changes channel, the driver and sampling capacitor must settle again, so usable per-channel rate can be lower than the simple aggregate-rate division.

Note

Example — Choosing and interpreting a sampling rate

For audio bandwidth $B=20\,\mathrm{kHz}$ sampled at $f_s=48\,\mathrm{kS/s}$,

$$T_s=20.833\,\mathrm{\mu s},\qquad f_N=24\,\mathrm{kHz},\qquad OSR=\frac{48}{2(20)}=1.2.$$

The interval from $20$ to $24\,\mathrm{kHz}$ is guard band rather than wanted audio bandwidth. A $30\,\mathrm{kHz}$ tone reaching the sampler aliases to $|30-48|=18\,\mathrm{kHz}$, so it cannot be removed digitally afterward. The analog anti-alias filter must suppress it before sampling.

A sample-and-hold (S/H), also called a track-and-hold, follows the input while its switch is closed, then stores one sampled voltage on a capacitor while the ADC makes its decisions. It discretizes time but does not itself quantize amplitude.

Sample-and-hold circuit and timing vocabulary. Aperture delay locates the actual sampling instant; latency extends until the corresponding code is valid.

Quantity	Definition	Why it matters
Track mode	Switch closed; $C_H$ follows the input	Driver must charge the ADC input network.
Acquisition time $t_{acq}$	Time to settle after entering track mode	Limits source resistance and multiplexing speed.
Aperture delay $t_{ap}$	Mean delay from sample command to actual hold instant	Shifts the effective sampling time.
Aperture jitter $\sigma_t$	Random uncertainty of the aperture instant	Converts input slew into voltage noise.
Droop rate	Held-voltage change caused by leakage	Creates error during a long conversion.
Hold step/pedestal	Output jump at track-to-hold transition	Caused mainly by switch charge injection.
Feedthrough	Input or clock coupling into the held node	Disturbs the supposedly constant sample.
Settling accuracy	Error band reached during acquisition	Must normally be below the allocated LSB fraction.

Sample-and-hold quantities.

For a simple first-order source resistance $R_s$ charging input capacitance $C_{in}$, settling from a full-scale step to within $\tfrac12$ LSB requires approximately

$$\boxed{t_{acq}\ge(n+1)\ln(2)\,R_sC_{in}}.$$

Real ADC data sheets include switch resistance, charge redistribution and driver recovery, so this is a design estimate rather than a replacement for the specified acquisition-time test.

Note

Key Point — Do not confuse

Bit count sets resolution, not guaranteed accuracy. Sampling rate is not always output throughput, conversion latency is not always one sample period, and a sample-and-hold freezes amplitude but does not quantize it.

ADC Specifications and Error Terms

ADC quality is described in three complementary ways: static transfer tests use slowly changing or DC inputs; dynamic tests use sampled sinusoids and spectra; timing/interface tests describe when a valid code appears and how quickly another conversion can begin.

Static transfer specifications

Specification	Meaning or relation	Design consequence
Resolution	$n$ bits, $2^n$ codes; $\Delta=V_{FS}/2^n$	Ideal granularity, not guaranteed accuracy
Input range/span	Allowed limits and $V_{FS}=V_{max}-V_{min}$	Must match signal, common-mode and reference limits
Transition voltage	Input at which one code changes to the next	Basic measured point for transfer testing
Quantization error	Ideally bounded by $\pm\Delta/2$ for midpoint rounding	Irreducible ideal amplitude uncertainty
Offset error	Horizontal shift of transfer characteristic	Produces nearly constant code error
Gain error	Full-scale slope error after offset removal	Reference/gain calibration can reduce it
DNL	Actual code width minus $1\,\mathrm{LSB}$	DNL$>-1\,\mathrm{LSB}$ prevents missing codes
INL	Deviation from an ideal straight transfer line	Limits absolute accuracy and distortion
Monotonicity	Code never decreases as input increases	Essential in control and closed-loop systems
Missing code	A nominal code has no positive-width input bin	Indicates local non-monotonic or zero-width behavior
Transition noise	Code spread under repeated conversion of one DC input	Sets code flicker and noise-free resolution
TUE	Worst total unadjusted error under stated conditions	Combines specified uncalibrated error contributions
Reference and temperature drift	Change of scale and errors with supply/temperature	Sets long-term calibration stability

Static ADC specifications.

Define endpoint boundaries $V_0=V_{min}$ and $V_L=V_{max}$, where $L=2^n$; for $1\le k\le L-1$, let $V_k$ be the actual transition from code $k-1$ to $k$. The width of code $k$, $0\le k\le L-1$, is $W_k=V_{k+1}-V_k$. Then

$$\boxed{DNL[k]=\frac{W_k}{\Delta}-1},\qquad \boxed{INL[k]=\frac{V_k-V_{k,ideal}}{\Delta}}.$$

INL must name its reference line (endpoint or best fit). A code is missing when $W_k\le0$, equivalently $DNL[k]\le-1$ LSB. If the peak-to-peak input-referred transition noise is $V_{n,pp}$, an approximate noise-free resolution is

$$N_{free}\approx\log_2\!\left(\frac{V_{FS}}{V_{n,pp}}\right),$$

provided the measurement bandwidth and test method are stated.

Static ADC errors relative to the dashed ideal transfer. Offset and gain change scale; DNL changes code widths; INL measures transfer curvature.

Offset and gain errors in detail

Note

Key Point — Ideal line versus ideal finite-resolution ADC

An infinite-resolution straight line is a conceptual analog reference. An ideal $n$-bit ADC still has a staircase because its resolution is finite; “ideal” means that its transition locations and code widths exactly follow the chosen quantizer convention. Static errors compare the measured staircase with that ideal finite-resolution staircase.

Offset error

Offset error translates the transfer characteristic horizontally without ideally changing the spacing between transitions. Using the transition-voltage sign convention adopted here,

$$\boxed{E_{OS,V}=V_{1,actual}-V_{1,ideal}}, \qquad \boxed{E_{OS,LSB}=\frac{E_{OS,V}}{\Delta}}, \qquad \boxed{E_{OS,\%FS}=100\frac{E_{OS,V}}{V_{FS}}}.$$

A positive value means the measured transition occurs at a larger input voltage (the staircase is shifted right). Some data sheets define polarity from code error rather than transition error and therefore reverse this sign; the stated convention must always be checked.

Applying zero input and observing a nonzero code is a useful quick test only for a compatible unipolar coding convention. Measuring the first specified transition is the more general definition. Digital subtraction can calibrate offset, but cannot recover analog headroom already lost by early clipping.

Gain error

Gain error is measured after offset removal. It changes the average slope or span of the transfer. One transition-based definition is

$$\boxed{E_{G,V}=V_{L-1,actual,corr}-V_{L-1,ideal}}, \qquad E_{G,LSB}=\frac{E_{G,V}}{\Delta}, \qquad E_{G,\%FS}=100\frac{E_{G,V}}{V_{FS}}.$$

Here “corr” means that the measured characteristic has first been translated to remove offset. A two-point calibration can correct offset and average gain, but any curvature, unequal code widths, noise and clipping remain.

Offset and gain errors measured from transition positions. Offset is removed first; gain error is then measured at the upper end of the transfer.

Note

Example — Offset and gain in three units

For a 12-bit, $0$–$5\,\mathrm{V}$ ADC,

$$\Delta=\frac{5}{4096}=1.2207\,\mathrm{mV}.$$

An offset of $4$ LSB equals

$$E_{OS,V}=4\Delta=4.883\,\mathrm{mV}, \qquad E_{OS,\%FS}=100\frac{4}{4096}=0.0977\%.$$

After offset correction, a gain error of $1.5$ LSB equals $1.831\,\mathrm{mV}$ or $0.0366\%$ of span. These conversions change the units, not the underlying error.

DNL, missing codes and monotonicity

Differential nonlinearity is a local width error. If one measured code bin has width $W_k=1.2\Delta$, then $DNL[k]=+0.2$ LSB; if $W_k=0.4\Delta$, then $DNL[k]=-0.6$ LSB. At $W_k=0$, $DNL[k]=-1$ LSB and code $k$ is missing.

Note

Law — No-missing-code condition

$$\boxed{DNL[k]>-1\ \mathrm{LSB}\quad\text{for every code}}$$

guarantees positive code widths and therefore no missing codes. The condition is not $|DNL|<1$: a wide code can have $DNL>+1$ without that code itself being missing. Monotonic output and no missing codes are related but distinct specifications; a monotonic converter can jump over a code.

INL and its relation to DNL

Integral nonlinearity is a global transition-position error. Before removing endpoint slope, the transition locations satisfy

$$V_k=V_0+\sum_{i=0}^{k-1}W_i, \qquad INL[k]=\sum_{i=0}^{k-1}DNL[i]$$

when the same $V_0$ and ideal $\Delta$ are used. Thus consecutive positive or negative DNL values accumulate into INL; isolated positive and negative DNL can partly cancel.

Two reference-line methods are common:

• Endpoint INL: Use the line through specified end transitions after offset/gain handling. It preserves endpoint meaning and is common in precision specifications.

• Best-fit INL: Choose a regression line that best fits all measured transitions. It usually reports a smaller numerical INL, so values from the two methods are not directly interchangeable.

Differential and integral nonlinearity. DNL measures each bin width; transition-based INL is the cumulative departure from the chosen ideal line.

Note

Key Point — Static LSB error is not ENOB

For a 12-bit ADC, $4$ of its own LSBs have the same voltage magnitude as one 10-bit LSB because $4=2^2$. This is a useful static-error scale comparison, but it does not prove “10-bit ENOB” or guarantee 10-bit total accuracy. ENOB comes from measured SINAD; absolute accuracy also includes offset, gain, INL, reference, noise, drift and loading. Likewise, a DNL limit cannot be converted directly into effective bit count.

Timing and dynamic specifications

Quantity	Definition	Important distinction
Sampling rate $f_s$	Sampling instants requested per second	Must satisfy anti-alias needs.
Throughput/output rate	Completed output words per second	Can differ from $f_s$ or inverse latency.
Conversion time $t_{conv}$	Time used internally to determine one code	Architecture dependent.
Latency	Delay from aperture instant to corresponding valid output	A pipeline may have high throughput but many-cycle latency.
Analog input bandwidth	Front-end frequency response before sampling	May exceed $f_s/2$; does not permit unplanned aliasing.
SNR	Fundamental signal power divided by noise power	Excludes harmonic distortion.
SINAD	Fundamental divided by noise plus distortion	Directly determines ENOB.
THD	RSS harmonic rms amplitude divided by fundamental amplitude	Measures nonlinearity, not random noise.
SFDR	Fundamental-to-largest-spur ratio	Does not integrate the entire noise floor.
ENOB	Equivalent ideal bit count from measured SINAD	Dynamic performance, usually frequency dependent.
Aperture jitter	RMS sampling-time uncertainty	Sets an SNR limit that worsens with $f_{in}$.

Timing and AC specifications.

For an ideal full-scale sinusoid and uncorrelated uniform quantization error,

$$\boxed{SNR_q\simeq6.02n+1.76\ \mathrm{dB}},\qquad \boxed{ENOB=\frac{SINAD-1.76}{6.02}},$$

while sampling-clock jitter imposes approximately

$$\boxed{SNR_j\simeq-20\log_{10}(2\pi f_{in}\sigma_t)}.$$

Note

Key Point — Static versus dynamic quality

DNL determines code-width uniformity and missing-code risk; INL measures overall transfer-line curvature. SNR counts noise, SINAD counts noise plus distortion, and ENOB converts measured SINAD into an equivalent ideal bit count.

This assumes an ideal ADC and sufficiently active codes; real SINAD also contains thermal noise, clock jitter, harmonic distortion and reference error. Resolution is therefore not the same as accuracy or effective resolution.

Note

Example — Aperture-jitter limit

For $f_{in}=100\,\mathrm{kHz}$ and rms aperture jitter $\sigma_t=1\,\mathrm{ns}$,

$$SNR_j=-20\log_{10}(2\pi f_{in}\sigma_t)=64.0\,\mathrm{dB}.$$

Jitter alone therefore limits the equivalent ideal resolution to about $(64.0-1.76)/6.02=10.3$ bits, even if the nominal ADC has more bits.

[!NOTE]

Example — Resolution, code and quantization error

A $12$-bit ADC has $V_{ref}=3.3\,\mathrm{V}$. Its step is

$$\Delta=\frac{3.3}{4096}=805.7\,\mathrm{\mu V}.$$

With a straight-binary truncating convention, $V_{in}=2.000\,\mathrm{V}$ gives $D=\lfloor V_{in}/\Delta\rfloor=2482=\mathtt{0x9B2}$. The code interval is $[2482\Delta,2483\Delta)=[1.999658,2.000464)\,\mathrm{V}$. Its midpoint is $2.000061\,\mathrm{V}$, so $q_e=-61.0\,\mathrm{\mu V}$. The ideal full-scale-sine SNR is $6.02(12)+1.76=74.0\,\mathrm{dB}$.

ADC Architecture Families

An ADC architecture is the internal method used to locate the input’s code bin. Parallel comparison minimizes decision time; feedback methods reuse one comparator; subranging resolves a few bits per stage; integration converts voltage to a time ratio; oversampling trades excess sample rate for in-band resolution.

Principal ADC families organized by the mechanism used to reach a code.

No architecture is universally best. Selection starts with signal bandwidth, required ENOB, latency, throughput, power, input loading, noise rejection and whether deterministic timing or absolute DC accuracy matters most.

Unless stated otherwise, the architecture equations and numerical examples below use a unipolar straight-binary range $0\le v_i<V_{ref}$ with $V_{min}=0$ and $\Delta=V_{ref}/2^n$. Bipolar designs shift the origin or select reference polarity according to their coding.

Flash (Parallel) ADC

A Flash converter generates all decision thresholds with a resistor string, compares the sampled input with every threshold simultaneously, and converts the resulting thermometer code to binary with a priority encoder. An $n$-bit converter requires

$$\boxed{N_C=2^n-1\ \text{comparators}},\qquad V_{Tk}=\frac{k}{2^n}V_{ref},\quad k=1,\ldots,2^n-1.$$

Three-bit Flash ADC: the ladder creates seven thresholds, the comparator bank produces a thermometer code, and the encoder returns a three-bit word.

Input interval	Comparators HIGH	Thermometer code	Binary output
$[0,V_{ref}/8)$	none
$[V_{ref}/8,2V_{ref}/8)$	$C_1$
$[2V_{ref}/8,3V_{ref}/8)$	$C_1,C_2$
$[3V_{ref}/8,4V_{ref}/8)$	$C_1$–$C_3$
$[4V_{ref}/8,5V_{ref}/8)$	$C_1$–$C_4$
$[5V_{ref}/8,6V_{ref}/8)$	$C_1$–$C_5$
$[6V_{ref}/8,7V_{ref}/8)$	$C_1$–$C_6$
$[7V_{ref}/8,V_{ref})$	$C_1$–$C_7$

Complete three-bit Flash conversion table; comparator order is $[C_7,C_6,\ldots,C_1]$, from highest to lowest threshold.

At an exact ideal threshold either adjacent code can appear depending on the specified transition convention; comparator offset and noise create a small real uncertainty region. Writing comparators in ascending order reverses every thermometer word, so the ordering must always be labelled.

All decisions occur in parallel, so Flash is the fastest architecture, requiring essentially one comparator-plus-encoder delay. The cost is exponential area, power and input capacitance: 8 bits require 255 comparators and 10 bits require 1023. Comparator offset, resistor mismatch and metastable “bubbles” limit accuracy, so Flash is normally low/medium resolution. Applications include oscilloscopes, video, radar and very-high-speed data acquisition.

Operating sequence and practical circuitry

1. Acquire and hold $v_i$ so every comparator sees the same voltage.

2. The $2^n$ equal ladder resistors create thresholds $\Delta,2\Delta,\ldots,(2^n-1)\Delta$.

3. All $2^n-1$ comparators resolve simultaneously. With $C_k=1$ for $v_i\ge V_{Tk}$, the ideal outputs form one monotonic run.

4. Bubble-correction logic removes sparse isolated comparator errors.

5. A leading-one/priority encoder finds the highest crossed threshold and latches its index as the binary output.

Practical comparator channels often contain a low-offset preamplifier, a fast regenerative latch and a retiming register before the encoder. Preamplification reduces latch kickback and input-referred offset; retiming aligns unequal comparator delays and confines metastability before deep logic.

A practical Flash comparator path and its latency components. Extra register stages can raise throughput but add clock-cycle latency.

With acquisition excluded from the internal decision time,

$$\boxed{t_{conv}\approx t_{cmp}+t_{bubble}+t_{enc}+t_{setup}}, \qquad \boxed{t_{lat}\approx t_{acq}+t_{conv}}.$$

An unpipelined converter’s maximum output rate is limited by this cycle. A registered or pipelined comparator/encoder tree may sustain a higher throughput while adding one or more clock cycles of latency.

If every resistor-string segment has resistance $R$,

$$R_{string}=2^nR, \qquad I_{lad}=\frac{V_{ref}}{2^nR}, \qquad P_{lad}=\frac{V_{ref}^2}{2^nR}.$$

If a fixed total resistance $R_T$ is chosen instead, each segment is $R_T/2^n$ and $I_{lad}=V_{ref}/R_T$. The signal driver sees roughly

$$\boxed{C_{in}\approx(2^n-1)C_{cmp}+C_{route}+C_{ESD}},$$

so comparator input capacitance and kickback also grow exponentially.

$n$ (bits)	3	4	6	8	10
Codes/resistors	8	16	64	256	1024
Comparators	7	15	63	255	1023

Full-Flash hardware growth.

Bubbles and metastability

An ideal thermometer code has only one zero–one boundary. Comparator offset, noise, reference kickback, unequal delay or input motion can create an isolated wrong bit called a bubble. Local majority logic such as

$$C'_k=\operatorname{maj}(C_{k-1},C_k,C_{k+1})$$

can repair a sparse one-bit bubble; robust encoders detect a valid run or boundary rather than trusting one comparator. This cannot repair grossly non-monotonic decisions or an input that changes too much during the aperture.

Flash-derived architectures

Interpolating Flash synthesizes intermediate thresholds from fewer physical preamplifiers. Folding reuses one comparator bank over coarse ranges. A two-step/subranging ADC resolves coarse bits, subtracts a DAC estimate, then resolves the residue. These reduce input capacitance, area and power at the cost of extra stages, calibration or latency.

Note

Example — Three-bit Flash decision

Let $V_{ref}=8\,\mathrm{V}$ and $v_i=5.2\,\mathrm{V}$. The seven thresholds are $1,2,\ldots,7\,\mathrm{V}$; the lower five comparators are high and the upper two low. In the figure’s descending threshold order, $[C_7,C_6,\ldots,C_1]=0011111$; in ascending order the same decisions are $[C_1,\ldots,C_7]=1111100$. The encoder outputs $101_2=5$, representing the interval $5$ to $6\,\mathrm{V}$.

Counter (Digital-Ramp) and Tracking ADCs

A counter ADC resets an $n$-bit counter to zero, converts each count through a DAC and increments until the comparator detects $V_{DAC}\ge v_i$. Its output is therefore the first trial code whose DAC value reaches the held input. With $V_{DAC}(D)=V_{min}+D\Delta$, this stop convention gives

$$D_{ramp}=\min\!\left(2^n-1, \left\lceil\frac{v_i-V_{min}}{\Delta}\right\rceil\right).$$

The explicit terminal-count clamp is essential because the largest ordinary DAC level is $V_{max}-\Delta$; without it, an input in the final bin would never satisfy $V_{DAC}\ge v_i$. Designs that latch the previous count produce the lower-edge floor convention instead.

Counter ADC feedback and its input-dependent DAC ramp. A tracking variant retains the previous code and moves one LSB per clock toward the input.

Conversion time depends on input amplitude:

$$T_{conv}\approx D T_{clk},\qquad \boxed{T_{wc}\approx(2^n-1)T_{clk}},$$

plus reset, acquisition and latch overhead. For uniformly distributed input codes, average search time is about $2^{n-1}$ clocks. The architecture is simple and low cost, but much slower than SAR because it performs a linear search instead of a binary search.

A tracking or servo ADC retains its previous code. An up/down counter increments when $v_i>V_{DAC}$ and decrements when $v_i<V_{DAC}$. It follows slowly varying inputs quickly but moves only one LSB per clock, so a basic tracking condition is

$$\boxed{\left|\frac{\mathrm{d}v_i}{\mathrm{d}t}\right|_{max}\lesssim\Delta f_{clk}}.$$

Rapid input steps require many clocks and comparator chatter can make the code toggle around one transition.

Note

Example — Counter-ADC conversion time

An 8-bit unipolar counter ADC has $V_{ref}=2.56\,\mathrm{V}$ and $f_{clk}=1\,\mathrm{MHz}$, so $\Delta=10\,\mathrm{mV}$. For $v_i=1.80\,\mathrm{V}$, the ramp reaches $D=180$ in approximately $180\,\mathrm{\mu s}$. Worst case is about $255\,\mathrm{\mu s}$, whereas an 8-bit SAR needs only eight trial clocks after acquisition.

Successive-Approximation (SAR) ADC

A successive-approximation-register ADC performs a binary search. It holds the input constant, tentatively sets one bit from MSB to LSB, converts that trial code back to analog, and retains or clears the bit according to one comparator decision. Conversion therefore has fixed duration independent of input value.

A SAR ADC uses comparator feedback to run a binary search; the trial code drives a DAC, represented here by a four-bit R–$2R$ ladder.

For straight-binary conversion, the trial DAC voltage is

$$\boxed{V_{DAC}=V_{ref}\left(\frac{b_{n-1}}2+ \frac{b_{n-2}}4+\cdots+\frac{b_0}{2^n}\right)}.$$

Modern SARs often use a binary-weighted capacitive array rather than R–$2R$, but the bit-test algorithm and ideal transfer are the same.

Conversion algorithm

1. Acquire and hold $v_i$; clear the register and assert start of conversion (SOC).

2. Tentatively set the MSB, giving $V_{DAC}=V_{ref}/2$.

3. If $v_i\ge V_{DAC}$ retain the bit; otherwise clear it.

4. Tentatively set the next bit while preserving earlier decisions. Repeat comparison through the LSB.

5. After $n$ decisions, latch the code and assert end of conversion (EOC).

The internal decision time is approximately

$$\boxed{t_{conv}\simeq nT_{clk}+t_{oh}}, \qquad \boxed{t_{cycle}\simeq t_{acq}+t_{conv}}.$$

The held input must not move enough to alter a decision during those trials.

Four-bit SAR conversion: a retained bit moves the trial upward; a cleared bit moves it downward, halving the remaining search interval each time.

Note

Example — Four-bit successive approximation

Let $V_{ref}=16\,\mathrm{V}$ and $v_i=10.4\,\mathrm{V}$, so $\Delta=1\,\mathrm{V}$. The trials are

$$\begin{array}{ccl} 1000 & \to8\,\mathrm{V}: & 10.4\ge8,\ \text{keep }b_3, \\ 1100 & \to12\,\mathrm{V}: & 10.4<12,\ \text{clear }b_2, \\ 1010 & \to10\,\mathrm{V}: & 10.4\ge10,\ \text{keep }b_1, \\ 1011 & \to11\,\mathrm{V}: & 10.4<11,\ \text{clear }b_0. \end{array}$$

Thus $D=1010_2$ identifies $[10,11)\,\mathrm{V}$: the midpoint convention gives $q_e=-0.1\,\mathrm{V}$, while lower-edge truncation gives $+0.4\,\mathrm{V}$. The four decisions take four trial clocks.

SAR offers an excellent speed, resolution, power and area compromise, commonly 8–18 bits. Its limits include S/H acquisition, reference settling, DAC matching/linearity, comparator offset/noise and clock feedthrough. Applications include microcontrollers, multiplexed sensor interfaces, data acquisition and digital instrumentation.

Pipeline and Two-Step ADCs

Half-flash (two-step subranging) ADC

A half-flash ADC, also called a two-step or subranging ADC, divides an $n$-bit conversion into a coarse Flash decision and a fine Flash decision. A DAC reconstructs the coarse result; the converter subtracts it from the same held input and quantizes the remaining residue to obtain the lower bits.

“Half-flash” means that the output bits are approximately divided between two Flash stages; it does not mean that the circuit uses exactly half as many comparators as a full Flash ADC. For an 8-bit design, a $4+4$ split is natural. The input must remain held while both decisions, the DAC reconstruction and the residue operation take place.

Ideal 8-bit half-flash (two-step subranging) ADC. The residue gain expands one coarse-code interval to the fine ADC’s full input range; without this $\times16$ block, the fine ADC must instead use a range of $V_{ref}/16$.

Main blocks and their roles

The conversion path contains seven functional blocks:

Block	Function
Sample-and-hold	Captures $v_i$ and keeps one value constant throughout both conversion steps.
Coarse 4-bit Flash	Locates the held input in one of 16 coarse ranges and produces the four MSBs $C$.
-bit DAC	Reconstructs the lower boundary $V_{DAC}$ of the selected coarse range.
Subtractor	Forms the residue $r=v_s-V_{DAC}$, the part not represented by the coarse code.
Residue amplifier	Usually multiplies $r$ by $16$ so one coarse interval occupies the fine Flash ADC’s full range.
Fine 4-bit Flash	Quantizes the scaled residue and produces the four LSBs $F$.
Delay/latches and logic	Delays the early MSBs, aligns both results and forms the final 8-bit word; practical designs may also correct redundant decisions.

Blocks in an 8-bit half-flash ADC.

General conversion law

Let the coarse stage resolve $m$ bits and the fine stage resolve $\ell$ bits, so $n=m+\ell$. For a unipolar input $0\le v_s<V_{ref}$,

$$\Delta=\frac{V_{ref}}{2^{m+\ell}}, \qquad \Delta_C=\frac{V_{ref}}{2^m}=2^\ell\Delta .$$

The ideal coarse conversion, DAC reconstruction and residue are

$$\boxed{C=\left\lfloor\frac{v_s}{\Delta_C}\right\rfloor}, \qquad \boxed{V_{DAC}=C\Delta_C}, \qquad \boxed{r=v_s-V_{DAC}},$$

where $0\le r<\Delta_C$. A residue gain $G=2^m$ expands this interval to the fine ADC’s full range:

$$r'=2^m r, \qquad \boxed{F=\left\lfloor\frac{r'}{V_{ref}/2^\ell}\right\rfloor =\left\lfloor\frac{r}{\Delta}\right\rfloor}.$$

The aligned result is the concatenation

$$\boxed{D=2^\ell C+F}.$$

For an ideal $4+4$ converter, $G=16$ and $D=16C+F$. If the residue is not amplified, the fine ADC must instead have full-scale span $\Delta_C=V_{ref}/16$; its local step is then $\Delta_C/16=V_{ref}/256$.

Step-by-step operation

1. Sample: the S/H acquires $v_i$ and enters hold mode.

2. Coarse conversion: the first 4-bit Flash ADC selects one of 16 coarse ranges and outputs $C$, the four MSBs.

3. Reconstruction: the DAC converts $C$ to the analog coarse estimate $V_{DAC}=C(V_{ref}/16)$.

4. Residue extraction: the subtractor forms $r=v_s-V_{DAC}$; ideally $0\le r<V_{ref}/16$.

5. Fine conversion: either $r$ is amplified by $16$ and applied to a full-range 4-bit Flash ADC, or an unamplified residue is applied to a fine ADC whose range is $V_{ref}/16$.

6. Alignment: latches retain the earlier MSBs until the LSBs are ready, then logic forms $D=C\,\|\,F=16C+F$.

Note

Key Point — Comparator-count advantage

A full 8-bit Flash converter requires

$$2^8-1=255\ \text{comparators}.$$

Two ideal 4-bit Flash stages require only

$$\boxed{N_C=2(2^4-1)=30\ \text{comparators}},$$

a reduction of $225$, or about $88.2\%$. This comparison counts only Flash comparators: the half-flash ADC additionally needs a DAC, subtractor/residue amplifier, timing and latches. Redundant practical stages can also require more than the ideal 30 comparators.

[!NOTE]

Example — Eight-bit half-flash conversion

Let $V_{ref}=16\,\mathrm{V}$, $v_i=12.35\,\mathrm{V}$ and use the chapter’s half-open, truncating code-bin convention. The final and coarse steps are

$$\Delta=\frac{16}{256}=0.0625\,\mathrm{V}, \qquad \Delta_C=\frac{16}{16}=1.0\,\mathrm{V}.$$

The coarse stage gives

$$C=\left\lfloor\frac{12.35}{1.0}\right\rfloor =12=1100_2, \qquad V_{DAC}=12.0\,\mathrm{V}.$$

Therefore

$$r=12.35-12.0=0.35\,\mathrm{V}, \qquad r'=16r=5.6\,\mathrm{V}.$$

The full-range fine 4-bit Flash has a $1\,\mathrm{V}$ step in the amplified domain, equivalent to $0.0625\,\mathrm{V}$ at the original input. Hence

$$F=\left\lfloor\frac{5.6}{1.0}\right\rfloor =5=0101_2,$$

and

$$\boxed{D=16(12)+5=197=11000101_2}.$$

Code 197 represents $[12.3125,12.3750)\,\mathrm{V}$, which contains the input. Its midpoint estimate is $12.34375\,\mathrm{V}$, giving $q_e=+6.25\,\mathrm{mV}$.

[!NOTE]

Key Point — Why the fine result is not rounded to 6

The ratio $0.35/0.0625=5.6$ identifies position within the coarse range. Under the transfer convention used throughout this chapter, the code is the bin index, so $F=\lfloor5.6\rfloor=5$. Rounding it to 6 would give total code 198, whose bin $[12.3750,12.4375)\,\mathrm{V}$ does not contain $12.35\,\mathrm{V}$. A problem that explicitly defines nearest-level thresholds may use a different code, but bin boundaries and reconstruction values must not be mixed.

Timing and practical errors

The decisions are sequential. A nonpipelined half-flash latency is approximately

$$\boxed{t_{2step}\simeq t_{coarse}+t_{DAC,res}+t_{fine}+t_{logic}},$$

where $t_{DAC,res}$ includes DAC, subtractor, residue-gain and settling time. Thus it is slower than a full Flash ADC but normally much faster than an $n$-step iterative converter. It cannot automatically accept one new sample per clock; interstage holding and pipelining are required to overlap conversions.

Important error sources are coarse-comparator offset and bubbles, coarse-DAC INL, subtractor offset, residue-gain error/nonlinearity, incomplete settling, S/H droop, reference mismatch and fine-comparator offset/noise. In a strict $4+4$ concatenation, a wrong coarse decision near a subrange boundary can move the output by 16 final LSBs. Practical converters therefore often provide overlap or redundant bits: the fine stage covers beyond one nominal coarse interval, and digital correction combines overlapping stage decisions. This tolerates bounded coarse-comparator and residue errors, but it does not fix arbitrary gross errors or an unsettled residue.

Half-flash ADCs offer much lower input capacitance, area and comparator power than full Flash at the same nominal resolution. Their costs are extra latency, a precision DAC/residue path, interstage matching and calibration complexity. They are useful in video, imaging, communication receivers and high-speed instrumentation where full Flash is too large or power hungry but SAR speed is insufficient.

Pipeline ADC

A pipeline ADC divides conversion among clocked stages. Each stage samples its input residue, resolves a few coarse bits with a small sub-ADC, converts those bits back through a sub-DAC, subtracts that estimate and amplifies the remaining residue for the next stage.

Pipeline ADC. Each stage resolves a few coarse bits, subtracts their DAC estimate, amplifies the residue and passes it to the next clocked stage.

For an ideal stage resolving $b$ bits,

$$\boxed{v_{res,next}=2^b\left(v_{res}-V_{DAC}\right)}.$$

Here $b$ is the integer gain exponent of a nonredundant ideal stage. The stage bits emerge on different clock cycles, so digital logic delays, aligns and combines them. A conventional “1.5-bit” stage has three decision regions, contributes roughly one effective bit and normally uses residue gain $2$, not $2^{1.5}$; its redundant range permits correction of finite sub-comparator offset.

Once all stages are full, a pipeline can deliver one conversion per clock even though one sample needs several clocks to traverse the chain:

$$\boxed{\text{throughput}\approx f_{clk}},\qquad \boxed{\text{latency}\approx N_{stages}T_{clk}}.$$

It therefore offers high throughput at medium/high resolution, but incurs multi-cycle latency, residue-amplifier settling and gain errors, sub-DAC linearity limits, clocking complexity and substantial analog power. Typical uses include video, intermediate-frequency digitization and high-speed data acquisition.

Note

Example — Pipeline throughput versus latency

A ten-stage ADC clocked at $100\,\mathrm{MHz}$ has a clock period of $10\,\mathrm{ns}$. Ignoring interface overhead, it can output one sample every $10\,\mathrm{ns}$ after filling, but the first result appears about $10(10\,\mathrm{ns})=100\,\mathrm{ns}$ after its sampling instant. Thus its throughput is $100\,\mathrm{MS/s}$ while latency is about ten cycles.

Single-Slope and Dual-Slope Integrating ADCs

An integrating ADC converts voltage into a measured time or count by using an op-amp integrator. A single-slope converter times one calibrated ramp; a dual-slope converter first integrates the unknown for a fixed time and then measures the time required by an opposite reference to return the integrator to zero.

Integrating conversion deliberately trades speed for averaging, high DC resolution and good rejection of periodic interference. It suits slowly varying measurements and instruments, especially digital multimeters, weighing systems and precision panel meters; it is generally unsuitable for high-bandwidth, continuous waveform acquisition.

Single-slope (ramp) ADC

A single-slope ADC resets an integrator to zero, applies a constant reference of known polarity, and times the resulting linear ramp until it reaches the unknown input. In the figure, the applied input is $-V_{ref}$, so an inverting integrator produces a positive ramp.

Single-slope ADC. A fixed-slope reference ramp is timed until it reaches the unknown input; the count changes if $R$, $C$, $V_{ref}$ or the clock period changes.

With the capacitor initially discharged,

$$v_r(t)=-\frac{1}{RC}\int_0^t(-V_{ref})\,\mathrm{d}\tau =\frac{V_{ref}}{RC}t.$$

The comparator changes state when $v_r(T)=v_i$, hence

$$\boxed{T=RC\frac{v_i}{V_{ref}}}.$$

If the clock period is $T_c$ and the counter records approximately $N=T/T_c$ pulses,

$$\boxed{N\simeq\frac{RC}{T_c}\frac{v_i}{V_{ref}}}, \qquad \boxed{v_i\simeq\frac{NT_cV_{ref}}{RC}}.$$

A larger input therefore needs a longer ramp time and produces a larger count; the ramp slope itself remains fixed during one conversion.

Controller sequence

1. Momentarily close the reset switch to discharge the integrating capacitor and clear the counter.

2. Apply $-V_{ref}$ to the integrator and open the clock gate while $v_r<v_i$.

3. Count clock pulses as the reference ramp rises linearly.

4. When $v_r$ reaches $v_i$, the comparator closes the gate; latch the count $N$ as the output code.

5. Reset the integrator and counter before the next conversion.

The simplicity is attractive, but its scale depends directly on several analog and timing quantities. For fixed $v_i$, small changes produce approximately

$$\boxed{\frac{\delta N}{N}\simeq \frac{\delta R}{R}+\frac{\delta C}{C} -\frac{\delta V_{ref}}{V_{ref}} -\frac{\delta T_c}{T_c}}.$$

Resistor/capacitor tolerance and temperature coefficient, capacitor ageing and leakage, reset residue, integrator offset, comparator offset and clock error all change the result. Conversion time is also input-dependent and approaches $2^nT_c$ near full scale when the ramp is calibrated for an $n$-bit count. These limitations make the basic single-slope ADC unsuitable for precision measurement without frequent calibration.

Note

Example — Single-slope count and component drift

Let $V_{ref}=5.0\,\mathrm{V}$, $R=100\,\mathrm{k\Omega}$, $C=0.1\,\mathrm{\mu F}$, $v_i=2.0\,\mathrm{V}$ and $f_{clk}=100\,\mathrm{kHz}$. Then $RC=10\,\mathrm{ms}$ and

$$T=10\,\mathrm{ms}\left(\frac{2}{5}\right)=4.0\,\mathrm{ms}, \qquad N=\frac{4.0\,\mathrm{ms}}{10\,\mathrm{\mu s}}=400.$$

If $C$ rises by $1\%$ while the input is unchanged, the ramp takes $4.04\,\mathrm{ms}$ and the count becomes approximately $404$. Interpreting that count with the nominal calibration gives a $1\%$ high reading, directly showing why a basic single-slope ADC has poor uncalibrated accuracy.

Dual-slope ADC

A dual-slope ADC removes the first-order dependence on $R$, $C$ and clock period by using the same integrator and clock in two opposite-slope phases. It first integrates the unknown input for a fixed run-up interval $T_1$, then applies a known opposite-polarity reference and counts the variable run-down interval $T_2$ required to return to zero.

Dual-slope ADC architecture and counter-controlled sequence: a fixed $M$-clock run-up followed by a measured $N$-clock run-down.

Phase 0: reset or auto-zero

The capacitor and counter are reset. Practical converters may also measure and store integrator/comparator offset during an auto-zero interval. Residual charge must be small enough that each conversion begins from the same initial state.

Phase 1: fixed-time run-up

The switch applies $v_i$ for a prescribed $M$ clock periods, $T_1=MT_c$; commonly $M=2^n$. For a constant positive input,

$$\boxed{V_1=-\frac{v_iT_1}{RC}}.$$

The integrator ramps negative. A counter overflow or timing register marks the end of exactly $M$ clocks, changes the input switch to $-V_{ref}$ and clears or restarts the run-down counter.

Phase 2: measured run-down

The opposite reference produces a positive slope. At time $t$ after run-down begins,

$$v_{int}(T_1+t)=V_1+\frac{V_{ref}}{RC}t.$$

The zero-crossing comparator keeps the clock gate open until $v_{int}(T_1+T_2)=0$. Therefore

$$-\frac{v_iT_1}{RC}+\frac{V_{ref}T_2}{RC}=0, \qquad \boxed{\frac{v_i}{V_{ref}}=\frac{T_2}{T_1}}.$$

With $T_1=MT_c$ and $T_2=NT_c$,

$$\boxed{v_i=V_{ref}\frac{N}{M}}.$$

For $M=2^n$, the latched run-down count is ideally $N\simeq2^n v_i/V_{ref}$. The nominal unipolar range remains half-open, $0\le v_i<V_{ref}$, so the largest valid $n$-bit count is $2^n-1$; an exact or larger full-scale input must be treated as overrange.

Note

Key Point — Why dual slope is more accurate

The same $R$ and $C$ multiply both phases and cancel from the ratio. The same clock period also cancels because $T_2/T_1=N/M$. This cancellation assumes that the integrator and clock remain sufficiently stable during one complete conversion. Reference accuracy, zero-crossing error, leakage, finite op-amp gain, dielectric absorption and switching transients do not cancel automatically.

Counter and switch sequence

1. Reset/auto-zero the integrator and counter.

2. Select $v_i$ and integrate for exactly $M$ clocks. With an $n$-bit timing counter, overflow after $M=2^n$ clocks can change the switch.

3. Select $-V_{ref}$, restart the counter at zero and continue clocking while the integrator output has not crossed zero.

4. At the zero crossing, close the clock gate and latch the run-down count $N$; compute or directly interpret $N/M=v_i/V_{ref}$.

Conversion time and resolution trade-off

Ignoring reset and auto-zero overhead,

$$\boxed{T_{conv}=T_1+T_2=(M+N)T_c}.$$

For $M=2^n$ and $0\le v_i<V_{ref}$,

$$\boxed{T_{wc}\simeq(2^{n+1}-1)T_c \approx2^{n+1}T_c}.$$

Each added bit approximately doubles the fixed run-up and worst-case conversion time at the same clock frequency. Increasing $f_{clk}$ reduces conversion time only until integrator settling, comparator response, switching and counter limits dominate.

Note

Example — Dual-slope conversion

A $12$-bit converter uses $V_{ref}=1.000\,\mathrm{V}$ and a fixed run-up of $M=4096$ clocks. If run-down lasts $N=3072$ clocks,

$$v_i=1.000\frac{3072}{4096}=0.750\,\mathrm{V}.$$

At a $1\,\mathrm{MHz}$ clock, $T_1=4.096\,\mathrm{ms}$, $T_2=3.072\,\mathrm{ms}$ and the ideal conversion interval is $7.168\,\mathrm{ms}$ before reset/auto-zero overhead.

[!NOTE]

Example — Resolution versus worst-case time

At $f_{clk}=10\,\mathrm{MHz}$, $T_c=0.1\,\mathrm{\mu s}$. The common worst-case approximation gives

$$T_{wc,12}\approx2^{13}(0.1\,\mathrm{\mu s}) =0.8192\,\mathrm{ms},$$

whereas

$$T_{wc,16}\approx2^{17}(0.1\,\mathrm{\mu s}) =13.1072\,\mathrm{ms}.$$

Increasing resolution from 12 to 16 bits multiplies the worst-case time by $2^4=16$ at the same clock rate.

Averaging and mains-noise rejection

For a time-varying input, run-up measures its average over $T_1$:

$$\overline v_i=\frac{1}{T_1}\int_0^{T_1}v_i(t)\,\mathrm{d}t, \qquad \boxed{\overline v_i=V_{ref}\frac{T_2}{T_1}}.$$

Rectangular integration has normalized magnitude response

$$\boxed{|H(f)|=\left|\frac{\sin(\pi fT_1)}{\pi fT_1}\right|},$$

with zeros at $f=k/T_1$ for nonzero integer $k$. Choosing $T_1=20\,\mathrm{ms}$ rejects ideal $50\,\mathrm{Hz}$ interference; choosing $16.667\,\mathrm{ms}$ rejects $60\,\mathrm{Hz}$. A $100\,\mathrm{ms}$ run-up contains five 50-Hz periods and six 60-Hz periods, so it ideally rejects both. This averaging explains the excellent mains-noise immunity of integrating meters, although noninteger-frequency interference and front-end saturation are not eliminated.

Feature	Single slope	Dual slope
Measured interval	Reference ramp until it reaches $v_i$	Reference run-down after fixed-time input integration
Ideal result	$N\simeq(RC/T_c)(v_i/V_{ref})$	$N/M=v_i/V_{ref}$
$R,C$ dependence	Direct scale error	Cancels to first order between phases
Clock dependence	Clock period sets scale	Common clock period cancels in $N/M$
Noise rejection	Little inherent averaging	Strong averaging; selectable notches at $k/T_1$
Conversion time	Input-dependent, up to about $2^nT_c$	$T_1+T_2$, up to about $2^{n+1}T_c$
Typical use	Simple low-cost conversion	DMMs and precision low-rate measurement

Single-slope versus dual-slope conversion.

Dual-slope conversion offers high resolution, excellent DC accuracy and strong periodic-noise rejection with modest analog hardware. Its limitations are low throughput, input-dependent latency, reference error, integrator leakage and finite gain, dielectric absorption, comparator offset, switching charge and auto-zero overhead. It is preferred for slowly changing signals where measurement reliability matters more than acquisition speed.

Sigma-Delta ($\Delta\Sigma$) ADC

A sigma-delta converter trades bandwidth for resolution. A high-rate feedback modulator produces a low-resolution, usually one-bit stream; a digital low-pass filter removes out-of-band quantization noise and a decimator reduces the rate to high-resolution output words.

A first-order sigma-delta ADC produces a high-rate one-bit stream, shapes quantization noise out of band, then filters and decimates the result.

For signal bandwidth $B$ and modulator rate $f_s$, the oversampling ratio is

$$\boxed{OSR=\frac{f_s}{2B}}.$$

The summer subtracts one-bit DAC feedback, the integrator accumulates this error (sigma operation), and the quantizer emits a pulse density representing input amplitude. A one-bit DAC is inherently monotonic because it has only two reference levels.

Oversampling spreads approximately fixed quantization-noise power across the wider Nyquist band; digital filtering retains only the small in-band fraction. Oversampling alone gains about $3\,\mathrm{dB}$ SNR whenever OSR doubles. A linearized first-order modulator has approximately

$$\boxed{Y(z)=STF(z)X(z)+(1-z^{-1})E(z)},$$

so its noise-transfer function has a zero at DC. Quantization noise is suppressed in band and pushed to high frequency; a first-order loop ideally gains about $9\,\mathrm{dB}$ in-band SNR per doubling of OSR. More generally, for ideal order $p$,

$$P_{q,\,in}\propto OSR^{-(2p+1)},\qquad \Delta SNR\simeq(6p+3)\,\mathrm{dB}$$

per doubling of OSR. The digital filter then rejects the shaped out-of-band noise and decimates to the required output rate.

Sigma-delta ADCs provide excellent linearity, noise rejection and 16–24-bit resolution with simple analog circuitry. Their limitations are restricted signal bandwidth, filter latency, clock-jitter sensitivity, digital complexity, idle tones and higher-order loop-stability concerns. They dominate audio, precision sensor and biomedical conversion.

Practical ADC Interface, Error Budget and Calibration

An ADC never operates in isolation. The signal source, anti-alias filter, driver, sampling network, reference, clock, supplies, printed-circuit layout and digital interface all contribute error or limit speed.

Practical ADC signal chain. Conversion accuracy depends on the source, driver, reference, clock, supplies, return paths and digital interface—not only on the nominal converter core.

Input range, polarity and common mode

A single-ended ADC measures one input relative to a common reference. A differential ADC measures

$$v_d=v_p-v_n, \qquad v_{CM}=\frac{v_p+v_n}{2}.$$

Both pins must remain inside their specified common-mode range even when $v_d$ is valid. Differential drive rejects common coupled noise and even-order distortion, but does not remove reference, mismatch or clock errors. Unipolar, bipolar, pseudo-differential and fully differential ranges must therefore be distinguished before assigning codes.

Driver, reference, clock and layout

• Input driver: Must charge the switched input capacitance within $t_{acq}$, absorb kickback, remain stable with the ADC load and preserve the required bandwidth and distortion.

• Anti-alias network: Sets the wanted passband and attenuates all unwanted energy that would fold below $f_s/2$. Its resistance and the ADC input capacitance also affect settling.

• Reference: Sets every transition voltage. Check absolute accuracy, noise density, temperature coefficient, output impedance, load-transient recovery and local bypassing.

• Clock: Its rms jitter limits high-frequency SNR; keep clock edges from coupling into the analog input and reference.

• Supplies and layout: Keep analog/reference loops short, provide local decoupling, control return-current paths and prevent digital output currents from sharing sensitive analog impedance.

Reference variation is a scale error. For a fixed output code interpreted as an analog estimate in a unipolar converter, a small reference change produces approximately

$$\frac{\delta\hat v_i}{\hat v_i}\simeq \frac{\delta V_{ref}}{V_{ref}}.$$

Input-referred white noise density $e_n$ integrated over effective noise bandwidth $B_N$ gives the useful estimate

$$V_{n,rms}\simeq e_n\sqrt{B_N}.$$

Error budgeting and calibration

For error contributions expressed in the same units at one operating point, a conservative worst-case bound and an independent-error estimate are

$$\boxed{E_{WC}=\sum_i|E_i|}, \qquad \boxed{E_{RSS}=\sqrt{\sum_iE_i^2}}.$$

Use worst-case addition when guaranteed limits must hold simultaneously; use root-sum-square only for sufficiently independent random terms. A two-point calibration can remove much of offset and gain error, but it cannot remove quantization, random noise, missing codes or detailed INL shape. Calibration conditions must remain representative of reference, temperature and loading.

Note

Example — Required bits and an error budget

A $0$–$5\,\mathrm{V}$ sensor requires no more than $2\,\mathrm{mV}$ ideal steps. Therefore

$$n\ge\left\lceil\log_2\frac{5}{0.002}\right\rceil=12, \qquad \Delta=\frac{5}{4096}=1.221\,\mathrm{mV}.$$

Suppose bounded offset, gain-at-operating-point and INL contributions are $0.5$, $0.8$ and $1.0$ LSB. Their guaranteed static sum is

$$E_{static,WC}=2.3\ \mathrm{LSB}=2.81\,\mathrm{mV}.$$

If independent driver, reference and ADC noise terms are $0.3$, $0.4$ and $0.6$ LSB rms, then only those random terms are combined statistically:

$$E_{noise,rms}=\sqrt{0.3^2+0.4^2+0.6^2} =0.781\ \mathrm{LSB}=0.954\,\mathrm{mV}.$$

The 12-bit step-size requirement is met, but guaranteed absolute accuracy is not automatically $2\,\mathrm{mV}$; calibration or a tighter converter/reference may still be required.

Architecture Comparison and Selection

Type	Decision method	Timing behavior	Representative bits	Best fit and principal limitations
Flash	All thresholds in parallel	Comparator + encoder delay; highest raw speed	–10	Scopes, radar, direct IF; exponential power, area, input capacitance and matching.
Half-flash	Coarse Flash, DAC/residue path, then fine Flash	Two sequential decisions plus residue settling	–12	Video and fast DAQ; far fewer comparators than Flash, but residue accuracy limits.
Counter / tracking	DAC feedback with linear up/down search	Input dependent; worst counter case $2^n-1$ clocks	–12	Simple controls and slowly varying signals; poor step response and low speed.
SAR	DAC feedback with MSB-to-LSB binary search	Fixed $n$ decisions plus acquisition	–20	General DAQ and MCUs; DAC/reference settling and acquisition limit accuracy/speed.
Pipeline	Coarse sub-ADC, sub-DAC subtraction and residue gain per stage	One output/clock after fill; multi-cycle latency	–16	Video and IF; residue gain/settling, calibration, clocking and analog power.
Single-slope	Fixed reference ramp timed to the input crossing	Input-dependent; up to about $2^n$ clocks	–12	Simple low-cost conversion; $RC$, ramp, comparator and clock drift limit accuracy.
Dual-slope	Fixed run-up, timed reference run-down	$T_1+T_2$; very slow but deterministic ratio	–22	DMMs/precision DC; strong mains rejection, leakage and reference drift.
Sigma-delta	Oversampled feedback, noise shaping and digital decimation	Many modulator clocks plus filter latency	–24	Audio/precision sensors; limited signal bandwidth, latency, idle tones and loop limits.

Practical comparison of the principal ADC architectures.

The bit ranges are representative, not hard physical boundaries. Process, calibration, bandwidth and power targets can move them substantially.

Scaling check: At $n=12$, Flash needs $4095$ comparators, two 6-bit Flash stages need only $126$ comparators before redundancy and correction hardware, a counter ADC can need $4095$ trial clocks, SAR needs $12$, and a filled pipeline can output one word per clock after its latency, and a dual-slope converter with $T_1=4096T_c$ can need nearly $8192$ clocks. The tabulated bit ranges are representative, not hard architectural limits.

Note

Key Point — Architecture choice

Choose Flash for minimum latency and modest bits; half-flash when comparator count and input loading must fall at the cost of a second decision and precise residue path; pipeline for sustained high throughput at more bits; SAR for the general-purpose speed–resolution–power compromise; counter/tracking or single-slope only when simplicity dominates; dual-slope for precise DC amid interference; and sigma-delta for maximum in-band resolution when bandwidth and latency can be traded away.

[!NOTE]

Example — Choosing an architecture from requirements

• $8$ bits at hundreds of MS/s with minimum latency: Flash or a Flash-derived/pipeline solution, depending power and input loading.

• $12$–$16$ bits for a multiplexed sensor at moderate speed: SAR.

• Stable high-resolution DC in $50/60\,\mathrm{Hz}$ interference: dual-slope.

• High-resolution audio or biomedical bandwidth with latency allowed: sigma-delta.

Architecture selection follows from bandwidth, ENOB, latency, throughput, power, input drive and noise-rejection requirements rather than bit count alone.

Reference Definitions and Architecture Mechanisms

Core definitions

Term	Definition
ADC	Circuit that samples an analog input, quantizes each held sample to one of finite levels and encodes the selected level as a digital word.
Bit depth	Number $n$ of bits in one output word; it provides $2^n$ possible codes.
Resolution	Smallest ideal code interval: $\Delta=V_{FS}/2^n$, also stated as $n$ bits or $100/2^n\%$ of span.
Reference voltage	Precision analog standard that establishes the ADC transfer scale and its ideal transition voltages.
Sampling rate	Number of sampling instants per second, $f_s=1/T_s$; its associated Nyquist frequency is $f_s/2$.
Quantization	Irreversible assignment of a continuous-amplitude sample to one finite code bin.
Quantization error	Difference between the actual sample and represented level; ideally $
Single-slope	Integrating ADC that counts the time for a fixed reference ramp to reach the unknown input; its scale depends on $RC$.
Dual-slope	Integrating ADC that applies the input for a fixed time, then counts an opposite-reference return to zero; $RC$ cancels ideally.
Half-flash	Two-step ADC that resolves coarse bits, subtracts their DAC value and quantizes the remaining residue for the fine bits.
Conversion time	Internal time needed to determine one result after conversion begins.
Latency	Time from sampling instant to availability of that sample’s valid output code.
Throughput	Number of completed output codes per second after any pipeline is full.
DNL / INL	Code-width error relative to 1 LSB / transition deviation from a specified ideal straight line.
ENOB	Number of ideal bits giving the measured SINAD: $(SINAD-1.76)/6.02$.

Core ADC definitions.

Architecture	Core mechanism
Flash	Parallel comparators test every threshold simultaneously, minimizing latency but requiring exponentially more hardware.
Half-flash	A coarse Flash/DAC stage forms a residue that a second Flash stage resolves, reducing comparators at the cost of residue settling.
Counter	A DAC code rises one LSB per clock until it crosses the input, so time depends on input and can approach $2^n-1$ clocks.
SAR	A feedback DAC performs an MSB-to-LSB binary search, giving a fixed $n$ comparator decisions.
Pipeline	Clocked stages resolve coarse bits and amplify residue, giving one output per clock after multi-cycle latency.
Single-slope	A fixed reference ramp is timed until it reaches the input; simple hardware leaves the result sensitive to ramp and clock scale.
Dual-slope	Fixed-time integration of the input followed by timed opposite-reference integration gives an accurate ratio and rejects periodic noise.
Sigma-delta	Oversampling and feedback shape quantization noise out of band; digital filtering and decimation recover high in-band resolution.

ADC architecture mechanism summary.