Counters

A counter is a sequential circuit that advances through a prescribed state sequence on clock events. The number of distinct states before the sequence repeats is its modulus. A mod-$N$ counter requires at least

$$\boxed{n=\lceil\log_2N\rceil}$$

flip-flops.

Type	Defining feature
Asynchronous or ripple	Only the first stage receives the external clock
Synchronous	Every stage receives one common clock
Up	State increases by one modulo $N$
Down	State decreases by one modulo $N$
Up/down	Direction input selects increasing or decreasing sequence
Mod-$N$	Repeats after exactly $N$ valid states
Decade	Mod-10; normally represents decimal digits 0–9

Counter classifications.

Asynchronous or Ripple Counters

In a ripple counter the external clock drives only the least-significant stage. Each later stage is clocked by an earlier output, so transitions do not occur simultaneously.

Two-bit asynchronous counter; clock bubbles specify falling-edge triggering.

For falling-edge T flip-flops with $T=1$ (or JK with $J=K=1$), connecting $Q_i$ to the next clock gives the up-count sequence

$$00\to01\to10\to11\to00.$$

Using $\overline Q_i$ instead gives the opposite direction for the same edge polarity. With positive-edge devices the required terminal reverses; verify the sequence rather than memorizing one connection.

Each stage divides frequency by two:

$$\boxed{f_{Q_i}=\frac{f_{clk}}{2^{i+1}}}.$$

The simple hardware is useful for low-speed counting and frequency division, but delay accumulates. A conservative estimate is

$$\boxed{t_{settle}\approx nt_{pd}},\qquad f_{max}\lesssim\frac{1}{nt_{pd}}.$$

During transitions such as $0111\to1000$, temporary intermediate codes can make an attached decoder glitch.

Synchronous Binary Counters

Every flip-flop receives the same clock. Combinational logic decides which bits toggle before the active edge.

Synchronous up counter

For T flip-flops,

$$T_0=1,\qquad \boxed{T_i=\prod_{j=0}^{i-1}Q_j}\quad(i\ge1).$$

Bit $i$ toggles when every lower bit is 1, the carry condition. For three bits,

$$T_0=1,\qquad T_1=Q_0,\qquad T_2=Q_1Q_0.$$

Synchronous down counter

A down-count bit toggles when all lower bits are 0, the borrow condition:

$$T_0=1,\qquad \boxed{T_i=\prod_{j=0}^{i-1}\overline Q_j}.$$

For three bits the sequence is

$$111\to110\to101\to100\to011\to010\to001\to000\to111.$$

Synchronous up/down counter

Let $U=1$ select up and $U=0$ select down. Then

$$\boxed{T_i=U\prod_{j=0}^{i-1}Q_j +\overline U\prod_{j=0}^{i-1}\overline Q_j}, \qquad T_0=1.$$

The direction input must meet setup and hold requirements like any other synchronous control.

Property	Ripple	Synchronous
Clock	External clock only at first stage	Common clock at every stage
State change	Propagates stage by stage	All stages sample together
Delay	Approximately cumulative $nt_{pd}$	Input logic plus one clock-to-$Q$ path
Transient codes	Common	Reduced, though decode hazards remain
Hardware	Minimal	Requires excitation logic
Best use	Divider or low-speed counter	High-speed and arbitrary counters

Ripple and synchronous counters compared.

Mod-$N$ and Decade Counters

If $N<2^n$, the unused states must be removed or redirected. A simple ripple implementation detects state $N$ and drives asynchronous clear.

Asynchronously truncated mod-10 (decade) counter.

The decade circuit counts 0000 through 1001. Arrival at $1010_2=10$ makes $Q_3Q_1=1$, so the NAND output clears all stages. The decoded state is brief; reset pulse width and decoder hazards must satisfy the flip-flop data sheet.

A synchronous mod-$N$ counter instead makes the last legal state advance directly to zero. This avoids a ripple-clear state but requires next-state logic.

Systematic Synchronous-Counter Design

1. Write the required sequence and choose $n=\lceil\log_2N\rceil$ state bits.

2. Form the present-state/next-state table and state a recovery policy for unused codes.

3. Use the selected flip-flop excitation table to obtain every input.

4. Simplify each input by Boolean algebra or Karnaugh map.

5. Draw one common clock and verify every legal and unused state.

Synchronous mod-5 example

For

$$000\to001\to010\to011\to100\to000,$$

one JK realization is

$$\boxed{J_2=Q_1Q_0,\ K_2=1},\qquad \boxed{J_1=K_1=Q_0},\qquad \boxed{J_0=\overline Q_2,\ K_0=1}.$$

Common-clock realization of the minimized synchronous mod-5 counter.

Using $Q^+=J\overline Q+\overline KQ$ gives

$$Q_2^+=Q_1Q_0\overline Q_2,\qquad Q_1^+=Q_1\oplus Q_0,\qquad Q_0^+=\overline Q_2\,\overline Q_0.$$

It also recovers from unused states: $101\to010$, $110\to010$, and $111\to000$.

Note

Key Point — Counter checks

State the edge polarity, count direction and modulus. Trace at least one wrap transition, check unused-state recovery, and include cumulative delay for a ripple design. A correct stable sequence can still produce decoder glitches during transitions.