Bipolar Transistor Switching Characteristics

A bipolar junction transistor (BJT) is a current-controlled, three-terminal device. In a switching circuit it is deliberately driven between cutoff (OFF, approximately an open circuit) and saturation (ON, approximately a closed switch). The forward-active region is useful for amplification, but in a switch it is crossed only during a transition.

Static Switching States

For the grounded-emitter NPN circuit in the figure, a HIGH input supplies base current and produces a LOW collector output. The stage is therefore both a switch and a logical inverter.

Grounded-emitter BJT switch and its inverted collector-output waveform.

Region	Junction bias	Useful relation	Switch interpretation
Cutoff	B–E is not forward biased; B–C is reverse biased	$I_B\simeq0$, $I_C\simeq I_{CEO}\approx0$, $V_{CE}\simeq V_{CC}$	OFF; open switch
Forward active	B–E forward biased; B–C reverse biased	$I_C=\beta I_B$ while the load permits it	Transition/amplifier region
Saturation	B–E and B–C both forward biased	$V_{CE}\simeq V_{CE(\mathrm{sat})}$, commonly $0.1$–$0.3\,\text{V}$	ON; closed switch with a small voltage drop

Bias conditions and terminal quantities in the three BJT regions.

Note

Key Point — A common correction

Cutoff does not require the base–emitter junction to be strongly reverse biased; it is enough that it is not forward biased enough to establish base current. Also, $I_C=\beta I_B$ must not be used after the collector current has become load-limited in saturation.

DC Load Line and Saturation Design

Applying KVL around the collector circuit gives

$$V_{CC}=I_C R_C+V_{CE} \quad\Longrightarrow\quad \boxed{I_C=\frac{V_{CC}-V_{CE}}{R_C}}.$$

Thus the DC load line joins the two intercepts $(V_{CE}=V_{CC},I_C=0)$ and $(V_{CE}=0,I_C=V_{CC}/R_C)$. Increasing base drive moves the operating point from cutoff toward saturation, as shown in the figure.

Representative BJT output characteristics and DC load line for $V_{CC}=5\,V$ and $R_C=1\,k\Omega$.

At the ON endpoint the load, not the transistor’s active-region gain, fixes the collector current:

$$I_{C(\mathrm{sat})} =\frac{V_{CC}-V_{CE(\mathrm{sat})}}{R_C}.$$

Because transistor gain varies widely with device, current and temperature, a designer chooses a conservative forced beta $\beta_F=I_{C(\mathrm{sat})}/I_B$, normally smaller than the guaranteed $\beta_{\min}$. Equivalently, an overdrive factor (ODF) may be specified:

$$I_B=\mathrm{ODF}\frac{I_{C(\mathrm{sat})}}{\beta_{\min}}, \qquad \beta_F=\frac{\beta_{\min}}{\mathrm{ODF}}, \qquad \mathrm{ODF}>1.$$

Caution

Key Formula — BJT switch-design relations

$$\boxed{ \begin{aligned} I_{C(\mathrm{sat})}&=\frac{V_{CC}-V_{CE(\mathrm{sat})}}{R_C},\\ I_B&=\mathrm{ODF}\frac{I_{C(\mathrm{sat})}}{\beta_{\min}},\\ R_B&=\frac{V_{IH}-V_{BE(\mathrm{sat})}}{I_B},\\ P_{Q,\mathrm{ON}}&\simeq V_{CE(\mathrm{sat})}I_{C(\mathrm{sat})}. \end{aligned}}$$

Choose the next lower standard $R_B$ if guaranteed saturation is essential, then verify that the driving gate can supply the resulting base current and that transistor current and power ratings are respected.

Dynamic Switching Characteristics

Switching is not instantaneous. Junction capacitances must be charged during turn-on, and excess minority-carrier charge accumulated in saturation must be removed during turn-off. The standard definitions use the 10% and 90% levels of the final collector current.

Input pulse and collector-current response showing the standard BJT switching-time construction. Since $v_o=V_{CC}-I_C R_C$, the collector voltage waveform is inverted.

Interval	Measurement definition	Main physical event
Delay $t_d$	Input transition to $I_C=0.1I_{C(\mathrm{sat})}$	Charging the B–E depletion/diffusion capacitances to establish conduction
Rise $t_r$	$I_C$ rises from 10% to 90%	Transit through the active region toward saturation
Storage $t_s$	Input is removed or reversed until $I_C$ first falls to 90%	Removal/recombination of excess base charge stored in saturation
Fall $t_f$	$I_C$ falls from 90% to 10%	Junction capacitances discharge and the transistor returns to cutoff

Definitions and physical origins of BJT switching times.

Caution

Key Formula — Timing identities

$$\boxed{t_{\mathrm{ON}}=t_d+t_r},\qquad \boxed{t_{\mathrm{OFF}}=t_s+t_f},\qquad t_{\mathrm{sw}}=t_d+t_r+t_s+t_f.$$

These are transition-time definitions, not an exact formula for the period of every switching circuit; settling time and required duty cycle may impose a larger practical period.

Stored Charge and Speed Improvement

When the transistor is overdriven, both junctions are forward biased and the base contains excess minority carriers. If the excess stored charge at the start of turn-off is $Q_s$ and a nearly constant reverse base current $I_{BR}$ removes it, the useful first-order design estimate is

$$\boxed{t_s\approx\frac{Q_s}{\lvert I_{BR}\rvert}}.$$

The exact logarithmic charge-control expression depends on the forward and reverse drive network; therefore $Q_s=I_B\tau$ or $t_s=\tau\ln(I_{BF}/I_{BR})$ should not be treated as universal identities. The robust conclusions are that deeper saturation increases $Q_s$, while stronger reverse drive removes it faster.

Method	Action	Trade-off or use
Schottky/Baker clamp	Clamps the B–C junction before it becomes strongly forward biased, preventing deep saturation	Greatly reduces $t_s$; used in Schottky TTL
Reverse base drive	Applies negative base current at turn-off to sweep out stored carriers	Fast turn-off, but the driver must tolerate bidirectional base current
Speed-up capacitor	Places a small capacitor across $R_B$ to deliver brief turn-on and turn-off current pulses	Reduces edge delay; must limit peak base current and ringing
Controlled overdrive	Uses only enough base current for guaranteed saturation	Balances low $V_{CE}$ against storage delay
Reduced carrier lifetime	Process treatment reduces recombination lifetime	Improves speed at the cost of increased leakage

Methods for reducing BJT switching time.

Note

Example — Design of a saturated transistor switch

An NPN switch has $V_{CC}=5\,V$, $R_C=1\,k\Omega$, $\beta_{\min}=50$, $V_{IH}=5\,V$, $V_{CE(\mathrm{sat})}=0.2\,V$ and $V_{BE(\mathrm{sat})}=0.7\,V$. Find $R_B$ for $\mathrm{ODF}=2$, and estimate ON-state transistor dissipation.

1. Load-limited collector current

$$I_{C(\mathrm{sat})}=\frac{5-0.2}{1\,000} =4.8\,mA.$$

2. Guaranteed base current

$$I_B=2\frac{4.8\,\mathrm{mA}}{50}=192\,\mu\mathrm{A}, \qquad \beta_F=\frac{4.8\,\mathrm{mA}}{192\,\mathrm{\mu A}}=25.$$

3. Base resistor and power

$$R_B=\frac{5-0.7}{192\,\mathrm{\mu A}}=22.4\,k\Omega.$$

A standard $22\,k\Omega$ resistor gives slightly more base current and is suitable. The transistor’s steady ON loss is

$$P_{Q,\mathrm{ON}}\simeq0.2(4.8\,\mathrm{mA})=0.96\,mW.$$

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Note

Key Point — BJT switch summary

• OFF: $I_C\approx0$ and $V_{CE}\approx V_{CC}$; ON: $V_{CE}\approx V_{CE(\mathrm{sat})}$ and current is load-limited.

• Never size a saturated switch from a typical $\beta$ alone; use a conservative forced $\beta$ or ODF.

• $t_{\mathrm{ON}}=t_d+t_r$ and $t_{\mathrm{OFF}}=t_s+t_f$.

• Storage time is usually the dominant saturated-BJT turn-off delay; prevent deep saturation or remove base charge actively to reduce it.