Sequence Generators

A sequence generator is a clocked circuit whose outputs pass through a prescribed repeating sequence. It may use a feedback shift register, a counter plus decoder or memory, or general next-state logic.

For the shift convention used here,

$$(Q_3,Q_2,Q_1,Q_0)^+=(D_{in},Q_3,Q_2,Q_1).$$

Writing the update equation avoids ambiguity about the words “left” and “right.”

Shift-Register-Based Generators

Ring generator

A ring generator feeds the last-stage output back without inversion:

$$D_{in}=Q_0.$$

With a one-hot initial state,

$$1000\to0100\to0010\to0001\to1000.$$

An $n$-stage ring has $n$ useful states. Its outputs directly provide $n$ one-hot phases, but the all-zero state is locked and initialization must load exactly one 1.

Johnson generator

A Johnson or twisted-ring generator feeds back the complement:

$$D_{in}=\overline Q_0.$$

Starting from zero,

$$\begin{aligned} 0000 & \to1000\to1100\to1110\to1111 \\ & \to0111\to0011\to0001\to0000. \end{aligned}$$

An $n$-stage Johnson generator has $2n$ valid states.

Feedback-register realizations of ring and Johnson sequence generators.

Property	Ring	Johnson
Feedback	$Q_{last}$	$\overline Q_{last}$
Useful states with $n$ FFs	$n$	$2n$
Pattern	One-hot bit circulates	1s fill, then 0s fill
Initialization	Preset one-hot word	Clear to zero
Decoding	Direct output	Two-input phase decoding
Risk	Zero lock or multiple circulating 1s	Invalid cycles
Use	One-hot timing and scanning	Multi-phase timing and control

Ring and Johnson generators compared.

Only $2n$ of the $2^n$ possible Johnson states belong to the intended cycle. Reset or recovery logic is required when deterministic startup matters.

Linear-Feedback Shift Register

An LFSR forms the serial input by XORing selected stage outputs. If the feedback polynomial is primitive and the seed is nonzero, an $n$-stage LFSR visits every nonzero state once:

$$\boxed{N_{max}=2^n-1}.$$

The all-zero state is locked because XOR of zeros remains zero.

For the primitive polynomial $p(x)=x^4+x+1$, use

$$\boxed{(Q_3,Q_2,Q_1,Q_0)^+ =(Q_1\oplus Q_0,Q_3,Q_2,Q_1)}.$$

Four-bit maximal-length LFSR realization.

Starting from 0001, the state sequence is

$$\begin{split} 0001 & \to1000\to0100\to0010\to1001\to1100\to0110\to1011 \\ & \to0101\to1010\to1101\to1110\to1111\to0111\to0011\to0001. \end{split}$$

The period is 15. The sequence is deterministic and is not cryptographically secure by itself. LFSRs are used for test patterns, scrambling, CRC hardware, spread-spectrum sequences and built-in self-test.

Counter-Based Sequence Generation

A binary or mod-$N$ counter can serve as a sequence address. A decoder asserts one timing output per count, while a ROM or combinational block maps each count to an arbitrary output word:

$$\boxed{Q_{counter}\longrightarrow \text{decoder/ROM}\longrightarrow Y_{sequence}}.$$

For a sequence of $M$ stored words, the address counter needs at least $\lceil\log_2M\rceil$ bits. This method is direct and easy to modify, but it uses more decoding or storage hardware than a short feedback pattern.

Design of a Required Sequence

For a repeating sequence of states:

1. assign a binary code to every required state;

2. write the present-state/next-state table, including unused-state policy;

3. choose flip-flops and derive their excitation or D-input equations;

4. simplify each equation and draw the common-clock circuit;

5. trace one full cycle plus every unused starting state.

Example: two-bit Gray sequence

Generate

$$00\to01\to11\to10\to00.$$

With two D flip-flops, the next-state table gives

$$\boxed{D_1=Q_0},\qquad \boxed{D_0=\overline Q_1}.$$

Design of the repeating two-bit Gray sequence. The next-state logic changes exactly one state bit on each clock edge.

Substitution verifies every transition. All four two-bit states are used, so there is no unused-state recovery case. If only an output waveform rather than the state word is required, decode the desired states after the register.

Method	Strength	Limitation
Ring	Direct one-hot phases	Only $n$ states from $n$ flip-flops
Johnson	$2n$ easily decoded phases	Invalid states need attention
LFSR	Period up to $2^n-1$ with few gates	Fixed pseudorandom order; zero lock
Counter + decoder/ROM	Arbitrary output sequence	Extra decoder or memory
Custom state machine	Arbitrary conditional sequence	Full state design required

Choosing a sequence-generator method.

Note

Key Point — Sequence verification

Never identify a generator only by its feedback sketch. State the shift direction, bit order, feedback equation and seed, then substitute states until the sequence repeats. Different drawing conventions can represent reciprocal feedback polynomials.