Amplifiers

Amplifier Fundamentals and Classification

An amplifier is an active circuit in which a small input signal controls energy drawn from a DC supply to produce a larger output signal. It does not create energy: its signal power gain is supplied by the DC source. For linear small-signal operation, the active device is biased at a quiescent point (Q point) and is operated over a region in which incremental relations are approximately linear.

Voltage, current and power gains are different port quantities:

$$A_v=\frac{v_o}{v_i},\qquad A_i=\frac{i_o}{i_i},\qquad A_p=\frac{P_o}{P_i}.$$

For sinusoidal signals at resistive ports,

$$|A_p|=|A_vA_i|,\qquad G_p=10\log_{10}A_p\ \text{dB}.$$

A voltage ratio is written as $G_v=20\log_{10}|A_v|$ dB. Interpreting that number as a power-gain comparison requires equal reference impedances; otherwise the impedance ratio must also be included. A CE or CS voltage gain is negative because the output is inverted, whereas power gain is quoted as a positive ratio.

Amplifiers may be classified by the amplified quantity (voltage, current, transconductance, transresistance or power), coupling (RC, direct or transformer), frequency range (audio, video/baseband, IF or RF), device connection, signal level and conduction class.

Untuned Amplifiers and Coupling Methods

An untuned amplifier provides useful gain over a continuous frequency band without using an LC resonator as its selective load. Untuned does not mean infinite or perfectly flat bandwidth: coupling and bypass capacitors usually set the low-frequency limit, while device, wiring and load capacitances set the high-frequency limit.

Stages are coupled to transfer signal while satisfying requirements for DC bias isolation, bandwidth, impedance matching, power transfer, size and distortion.

RC, direct and transformer coupling

RC coupling

An interstage capacitor passes AC but blocks DC, so adjacent Q points remain substantially independent. Its reactance increases at low frequency and forms a high-pass network with the surrounding resistances. RC coupling is cheap, compact and gives useful broadband voltage gain, but it provides poor impedance matching and is unsuitable for direct high-power transfer to a low resistance.

Direct coupling

A conductive connection passes both DC and AC, so response can extend to $0\,\text{Hz}$. It is natural in ICs, op-amps, differential stages and sensor interfaces. Its disadvantages are propagation of offset and drift, interaction of stage bias points and the possible need for level shifting.

Transformer coupling

AC transfers magnetically while DC is isolated. For an ideal transformer,

$$\frac{V_s}{V_p}=\frac{N_s}{N_p},\qquad \frac{I_s}{I_p}=\frac{N_p}{N_s},\qquad R_L'=\left(\frac{N_p}{N_s}\right)^2R_L.$$

The turns ratio can therefore present a suitable load to a transistor and a centre-tapped winding can phase-split a push-pull drive. Transformer coupling is bulky and costly; winding resistance, core loss and nonlinearity, leakage inductance and interwinding capacitance limit efficiency and bandwidth.

Qualitative native comparison of RC-, transformer- and direct-coupled frequency responses. Actual cutoffs depend on the circuit.

Property	RC	Direct	Transformer
Transfers DC	No	Yes	No
Low-frequency limit	Coupling/bypass capacitance	Can include DC	Magnetising inductance and core
Stage-bias isolation	Good	Poor	Excellent
Impedance matching	Poor	Not inherent	Excellent by turns ratio
Typical use	Audio and general voltage stages	Op-amps, sensors and ICs	Power output, isolation and matching
Main limitation	Low-$f$ roll-off and weak power matching	Offset and thermal drift propagate	Bulk, cost, loss and restricted bandwidth

Selection of an interstage coupling method.

CE RC-Coupled Amplifier

A common-emitter RC-coupled stage combines voltage-divider bias, a resistive collector load and capacitors that preserve DC bias while carrying the wanted AC signal.

Complete loaded CE RC-coupled amplifier with input/output coupling and emitter-bypass capacitors.

Component	Function
$R_1,R_2$	Establish a reasonably stiff base-bias voltage.
$R_C$	Converts collector-current change into an inverted voltage change.
$R_E$	Provides DC degeneration and stabilises current against $\beta$ and temperature variation.
$C_E$	Bypasses $R_E$ over the intended AC band to recover voltage gain.
$C_i,C_o$	Pass AC while blocking source/base and collector/load DC levels.
$R_L$	Receives output signal power and loads $R_C$ for AC.

Function of each component in the figure.

DC bias and signal operation

At DC, $C_i,C_o$ and $C_E$ are open. When divider current is large compared with base current,

$$V_B\simeq V_{CC}\frac{R_2}{R_1+R_2},\qquad V_E\simeq V_B-V_{BE},\qquad I_E\simeq\frac{V_E}{R_E}.$$

The Q point is chosen in the active region with enough headroom for the desired approximately symmetrical collector-voltage swing. Exact divider-bias analysis uses the Thevenin source $V_{TH}=V_{CC}R_2/(R_1+R_2)$ and $R_{TH}=R_1\parallel R_2$ so that base-current loading is included.

On a positive input half-cycle, $v_{BE}$ and $i_C$ increase. The drop across $R_C$ increases and $v_C=V_{CC}-i_CR_C$ falls. On the negative half-cycle the opposite occurs. The collector output is therefore amplified and shifted by approximately $180^\circ$.

Midband small-signal gain and loading

At room temperature,

$$g_m=\frac{I_C}{V_T},\qquad r_e\simeq\frac{V_T}{I_E}\simeq\frac{26\,\text{mV}}{I_E},\qquad r_\pi=\frac{\beta_{ac}}{g_m}.$$

Let $R_C'=R_C\parallel R_L\parallel r_o$. If $C_E$ is an AC short, the emitter is at AC ground, and the signal is defined at the base,

Caution

Key Formula — Loaded Midband CE Gain

$$\boxed{A_v=\frac{v_o}{v_b}\simeq-g_mR_C' \simeq-\frac{R_C'}{r_e}}.$$

If $r_o$ is neglected, omit it from $R_C'$. If $R_E$ is not bypassed and $\beta$ is large, a useful approximation is

$$A_v\simeq-\frac{R_C\parallel R_L}{r_e+R_E}.$$

With $R_B=R_1\parallel R_2$,

$$R_{in}\simeq R_B\parallel r_\pi,\qquad R_{out}\simeq R_C\parallel r_o.$$

Thus a finite source resistance gives the source-to-load gain

$$\frac{v_o}{v_s}\simeq \left(-g_mR_C'\right)\frac{R_{in}}{R_s+R_{in}}.$$

The intrinsic transistor current ratio $i_c/i_b\simeq\beta_{ac}$ is not the overall load-current gain $i_L/i_s$: bias-network current, source attenuation and collector/load current division must be included. For RMS quantities at resistive input and output ports,

$$A_p=\frac{P_o}{P_i}=|A_v|^2\frac{R_{in}}{R_L} =|A_vA_i|,$$

provided all port voltage/current definitions are used consistently.

Low-, mid- and high-frequency regions

Native three-region response of a practical RC-coupled CE stage.

Low frequency

As $f$ falls, $X_C=1/(2\pi fC)$ rises. The input and output capacitors attenuate signal transfer, while incomplete $C_E$ bypass increases emitter degeneration. Useful first estimates are

$$\begin{aligned} f_{Li}&\simeq\frac{1}{2\pi(R_s+R_{in})C_i},\nonumber\\ f_{Lo}&\simeq\frac{1}{2\pi(R_{out}+R_L)C_o},\nonumber\\ f_{Le}&\simeq\frac{1}{2\pi R_{E,seen}C_E},\qquad R_{E,seen}\simeq R_E\parallel \left(r_e+\frac{R_s\parallel R_B}{\beta_{ac}+1}\right). \end{aligned}$$

Other independent sources and capacitors are set to their small-signal conditions when finding each resistance. The combined $f_L$ is not simply the largest individual pole when two or more poles are close.

Midband

$C_i,C_o,C_E$ are approximately short circuits for signal, while device and stray capacitances are approximately open. Gain is nearly constant and the midband model leading to the equation applies.

High frequency

Base-emitter diffusion capacitance $C_\pi$, collector-base capacitance $C_\mu$, wiring capacitance and load capacitance shunt signal and introduce phase lag. In an inverting high-gain stage, Miller multiplication of $C_\mu$ is often the dominant mechanism.

At either overall cutoff,

$$|A_v|=\frac{|A_{v,mid}|}{\sqrt{2}}=0.707|A_{v,mid}|, \qquad BW=f_H-f_L.$$

This is a $-3.01$ dB voltage ratio and, for the same load, one-half of midband output power. Only when $f_H\gg f_L$ may one use $BW\simeq f_H$.

Miller effect

Native Miller transformation of the base-collector feedback capacitance into input- and output-referred capacitances.

Because the capacitor current is

$$i_\mu=C_\mu\frac{d(v_i-v_o)}{dt} =C_\mu(1-A_v)\frac{dv_i}{dt},$$

the source sees

Caution

Key Formula — Miller Input Capacitance

$$\boxed{C_{Mi}=C_\mu(1-A_v)}.$$

For a CE stage $A_v<0$, so

$$\boxed{C_{Mi}=C_\mu(1+|A_v|)},\qquad C_{Mo}=C_\mu\left(1-\frac{1}{A_v}\right).$$

The physical capacitor has not changed; output motion increases the current that the input source must supply.

An approximate total input capacitance and its pole are

$$C_{Hi}\simeq C_\pi+C_{wi}+C_\mu(1+|A_v|),\qquad f_{Hi}\simeq\frac{1}{2\pi R_{Hi}C_{Hi}},$$

where $R_{Hi}\simeq R_s\parallel R_1\parallel R_2\parallel r_\pi$. Miller effect lowers high-frequency input impedance, reduces $f_H$, slows rise time (approximately $t_r\simeq0.35/f_H$ for a dominant pole), and adds phase lag. It can be mitigated by a cascode, a device with smaller $C_\mu$, lower gain per stage, or neutralisation. A lower source resistance raises the input pole but does not reduce the Miller-equivalent capacitance itself.

Power Amplifiers

Definition	Concept / overview	Construction
Working	Derivation	Advantages
Disadvantages	Applications	Pitfall
Tip	Key point	Mnemonic

Text is meaning-coded too: definition, key/important, advantage, disadvantage, application. Each block also has a distinct icon, so the meaning survives greyscale printing.

What is a Power Amplifier?

A power amplifier is a large-signal amplifier — usually the final stage of a multistage system — whose job is to deliver a large amount of power to a low-impedance load such as a loudspeaker, motor, servo, or antenna. It is designed to maximise output power and efficiency, not voltage gain.

• Large-signal operation: it handles big voltage and current swings, so the device moves over a large part of its load line (unlike a small-signal voltage amplifier).

• Provides current/power gain: the preceding voltage amplifier supplies a large voltage; the power stage supplies the current needed to drive a low-$Z$ load.

• Key design concerns: output power, efficiency $\eta$, power dissipation / heat (heat sinks, thermal runaway), distortion (large-signal non-linearity), and impedance matching to the load.

• Figure of merit — efficiency:

$$\eta=\dfrac{P_{ac}\ (\text{power delivered to load})} {P_{dc}\ (\text{power drawn from supply})}\times 100\%$$

the rest of the DC power becomes heat in the device.

	Voltage (small-signal) amp	Power (large-signal) amp
Goal	high voltage gain	high output power + efficiency
Signal	small	large
Load line	small portion used	large portion used
Load $Z$	high	low (e.g. 4 $\Omega$–8 $\Omega$ speaker)
Output power	milliwatts	watts
Main worry	gain, noise	heat, efficiency, distortion

How power amplifiers are classified

• By conduction angle / biasing $\to$ Class A ($360^\circ$), Class B ($180^\circ$), AB, C ($<180^\circ$).

• By operating mode $\to$ Class D (switching / PWM).

• By coupling $\to$ RC-coupled, transformer-coupled, direct-coupled.

• By frequency $\to$ audio-frequency (AF) or radio-frequency (RF).

The conduction angle $\theta_c$ = the part of the $360^\circ$ input cycle during which the output device actually conducts current.

One-cycle waveform comparison

Conduction intervals and representative output waveforms for amplifier classes A, B, AB, and C.

Note

Key Concept — How to read this comparison

For Classes A/B/AB/C, the middle column is the current in one active device; this waveform defines the conduction angle. It is not always the final load voltage. Push–pull action (B/AB) or a tuned $LC$ tank (C) reconstructs the load waveform. For Class D, the middle column is the bridge switch-node PWM voltage and the right column is its filtered output. Waveforms are normalised; phase inversion depends on the circuit topology.

Class A Amplifier

Note

Key Concept — In one line

The transistor conducts for the full $360^\circ$ of the input cycle and is never cut off — giving the lowest distortion but the poorest efficiency.

[!NOTE]

Construction

• Uses a single transistor in the output stage.

• Biased (usually by a voltage-divider $R_1,R_2$ with an emitter resistor $R_E$) so the Q-point sits at the centre of the DC load line: $V_{CEQ}\approx V_{CC}/2$.

• Load can be directly/RC-coupled (series-fed) or transformer-coupled (to match the low-$Z$ speaker and raise efficiency).

• Because current flows continuously, it needs a heat sink even when idle.

Series-fed class-A power-amplifier circuit.

Series-fed (RC-coupled) Class A stage with voltage-divider bias.

Note

Working

• With the Q-point at mid-line there is a large quiescent current $I_{CQ}$ flowing even with no input signal.

• On the positive half-cycle the collector current rises above $I_{CQ}$; on the negative half-cycle it falls below $I_{CQ}$ — but never reaches zero (cut-off) and never hits saturation.

• Hence the device conducts for the entire $360^\circ$ and the output is a complete, faithful replica of the input $\Rightarrow$ no crossover distortion, very low harmonic distortion.

Class-A collector-current and output-voltage waveforms over a complete cycle.

$i_C$ never reaches zero — conduction over the whole cycle.

Note

Derivation — Power & Efficiency

(a) Series-fed / direct-coupled resistive load.
Major steps: $P_o=\tfrac12 V_{pk}I_{pk}$ $\xrightarrow{\text{Q mid-line}}$ $V_{pk}=\tfrac{V_{CC}}{2},\ I_{pk}=\tfrac{V_{CC}}{2R_C}$ $\Rightarrow$ $P_{o(\max)}=\tfrac12\!\cdot\!\tfrac{V_{CC}}{2}\!\cdot\!\tfrac{V_{CC}}{2R_C}=\tfrac{V_{CC}^{2}}{8R_C}$.

• AC output power delivered to the load:

$$P_o=V_{ce(\mathrm{RMS})}\,I_{c(\mathrm{RMS})}=I_{c(\mathrm{RMS})}^{2}R_C$$

• For a sinusoid $V_{\mathrm{RMS}}=V_{\mathrm{pk}}/\sqrt2$, so $P_o=\tfrac12 V_{o(\mathrm{pk})}I_{o(\mathrm{pk})}$. With Q at mid-line the largest symmetric swing has peaks $V_{o(\mathrm{pk})}=V_{CC}/2$ and $I_{o(\mathrm{pk})}=V_{CC}/2R_C$, hence

$$P_{o(\max)}=\tfrac12\cdot\dfrac{V_{CC}}{2}\cdot\dfrac{V_{CC}}{2R_C} =\dfrac{V_{CC}\,(V_{CC}/R_C)}{8}=\dfrac{V_{CC}^{2}}{8R_C}$$

The factor 8 is $2\times2\times2$: the first factor comes from $P_o=\tfrac12V_{\mathrm{pk}}I_{\mathrm{pk}}$, and the other two come from the half-supply voltage and current peaks. Equivalently, use (peak-to-peak $V_{CE}\times I_C$)$/8$.

• DC input power (with $I_{CQ}=V_{CC}/2R_C$):

$$P_i=V_{CC}\,I_{CQ}=\dfrac{V_{CC}^{2}}{2R_C}$$

• Efficiency $=$ (max AC out)$/$(DC in):

$$\eta_{\max}=\dfrac{P_{o(\max)}}{P_i} =\dfrac{V_{CC}^{2}/8R_C}{V_{CC}^{2}/2R_C}=\dfrac 14=25\%$$

(b) Transformer-coupled load. The primary has negligible DC resistance, so the quiescent current wastes almost no power $\Rightarrow$ higher efficiency.

• AC power in the primary — same $P_o=\tfrac12 V_{pk}I_{pk}$ as in (a), just with each peak written as (max$-$min)$/2$: $V_{pk}=\tfrac{V_{CE(\max)}-V_{CE(\min)}}{2}$, $I_{pk}=\tfrac{I_{C(\max)}-I_{C(\min)}}{2}$, hence

$$P_o'=\dfrac{[V_{CE(\max)}-V_{CE(\min)}]\,[I_{C(\max)}-I_{C(\min)}]}{8}$$

Load power $P_o=V_{2(\mathrm{RMS})}^{2}/R_L\approx P_o'$ (transformer $\eta>90\%$).

• Efficiency $=P_o'/P_{dc}$, with $P_{dc}=V_{CC}I_{CQ}$. Since Q is the mid-point of each swing, $V_{CC}=\tfrac{V_{CE(\max)}+V_{CE(\min)}}{2}$ and $I_{CQ}=\tfrac{I_{C(\max)}+I_{C(\min)}}{2}$, so

$$\eta=\frac{P_o'}{P_{dc}}=\frac12\cdot \frac{V_{CE(\max)}-V_{CE(\min)}}{V_{CE(\max)}+V_{CE(\min)}}\cdot \frac{I_{C(\max)}-I_{C(\min)}}{I_{C(\max)}+I_{C(\min)}}$$

(the $\tfrac12=\tfrac{1/8}{1/4}$ from $P_o'$ and $P_{dc}$). With the current swinging almost to cut-off ($I_{C(\min)}\!\approx\!0$, so the current ratio $\approx1$) this leaves the working form

$$\eta\approx 50\!\left(\dfrac{V_{CE(\max)}-V_{CE(\min)}} {V_{CE(\max)}+V_{CE(\min)}}\right)\%$$

(Some texts assume $i\!\propto\!v$ instead, giving the squared form $50(\cdots)^2\%$; both hit 50% at full swing.)

• Ideal limit ($V_{CE(\min)}\!\to\!0,\ V_{CE(\max)}\!\to\!2V_{CC}$): $\eta_{\max}=50\%$ — twice the series-fed value.

Class A push–pull (transformer-coupled)

Transformer-coupled push-pull class-A amplifier.

The transformer-coupled Class A push–pull amplifier drives alternate halves of the output transformer from the two active devices.

Note

Key Concept — How it works (few lines)

• $R_1,R_2$ (divider bias): set a fixed base $Q$-point in the middle of the active region, applied to both bases via the $T_1$ centre tap $\Rightarrow$ each transistor conducts the full $360^\circ$ (Class A).

• $T_1$ (centre-tapped) splits $v_i$ into two anti-phase drives $v_{i1},v_{i2}$; $T_2$ (centre-tapped) recombines the collector currents $I_{c1},I_{c2}$ into $R_L$.

• Even harmonics cancel by push–pull symmetry $\Rightarrow$ clean output (dominant residual $=$ 3rd harmonic).

• DC currents oppose in $T_2$ $\Rightarrow$ no core saturation (smaller core); $V_{CC}$ hum cancels; delivers up to $2\times$ the power of a single-ended Class A stage.

[!NOTE]

Exam Pitfall — Hottest at idle

In Class A the maximum device dissipation occurs at zero signal ($P_{D}=V_{CEQ}I_{CQ}$). As the signal grows, more power goes to the load and the transistor actually runs cooler. It wastes the most power when doing nothing.

[!NOTE]

Advantages

• Simplest output stage (single device).

• Best linearity / fidelity; lowest distortion; no crossover distortion.

• Good high-frequency behaviour.

[!NOTE]

Disadvantages

• Very low efficiency (25 % / 50 %).

• Large standing (quiescent) power wasted as heat $\Rightarrow$ big heat sink.

• Output transformer (if used) is bulky, costly, and can add frequency distortion.

[!NOTE]

Applications

• Small-signal / driver stages and preamplifiers.

• High-fidelity audio where quality matters more than efficiency.

• Low-power output stages.

Class B Amplifier

Note

Key Concept — In one line

Two transistors in push–pull, each conducting for only one half-cycle ($180^\circ$) — much higher efficiency than Class A, at the cost of crossover distortion.

[!NOTE]

Construction

• Uses two transistors in a push–pull pair, each biased at cut-off ($I_{CQ}\approx0$) — no forward bias.

Three standard push–pull arrangements:

1. Transformer-coupled: a centre-tapped input transformer splits the drive into two anti-phase halves; a centre-tapped output transformer recombines the two collector currents into the load.

2. Complementary-symmetry: a matched NPN + PNP pair on a dual supply $+V_{CC}/-V_{CC}$ — no transformer needed.

3. Quasi-complementary: uses two matched NPN output devices (driven by a small complementary pair), avoiding a costly high-power PNP; the most popular practical form.

Transformer-coupled push-pull class-B amplifier.

The transformer-coupled push–pull Class B amplifier uses alternate half-cycles to drive the output transformer.

Complementary-symmetry class-B output stage.

The complementary-symmetry Class B stage uses opposite transistor polarities to source and sink load current.

Quasi-complementary class-B output stage.

In the quasi-complementary Class B stage, $Q_1$–$Q_3$ form the upper Darlington pair while $Q_2$–$Q_4$ form the lower complementary-feedback (Sziklai) pair.

The Sziklai pair combines a small PNP driver with an NPN power transistor to behave as a high-gain PNP-like composite device.

Complementary-feedback Sziklai transistor pair and its composite PNP equivalent.

Note

Key Point — What is the “feedback pair”?

• Connections: $Q_2$ collector drives the $Q_4$ base; $Q_2$ emitter and $Q_4$ collector join at $v_o$; $Q_4$ emitter goes to ground (or the negative rail).

• Negative half-cycle: lowering the $Q_2$ base makes $V_{EB2}=v_o-v_{B2}$ large enough to turn $Q_2$ on. Its collector supplies $Q_4$ base current, so $Q_4$ sinks load current.

• Why feedback? As $Q_4$ pulls $v_o$ downward, the $Q_2$ emitter also falls. Therefore $V_{EB2}$ falls and $Q_2$ reduces the drive to $Q_4$: this is local negative feedback.

• Equivalent PNP: composite base $=Q_2$ base, composite emitter $=v_o$, composite collector $=Q_4$ emitter. Thus a small PNP driver controls a rugged NPN power transistor as a high-gain PNP-like device.

[!NOTE]

Exam Pitfall — Connection to remember

It is not $Q_4$ emitter tied to $Q_2$ emitter. The feedback/output node is $Q_2\text{ emitter}=Q_4\text{ collector}=v_o$; $Q_4$ emitter is the composite collector and returns to ground or the negative supply. The Sziklai pair behaves like a PNP stage, but it is not a perfect electrical copy of the upper Darlington pair.

[!NOTE]

Working — Operation of Figure 16.42

• Bias and input coupling: $R_1$–$R_3$ establish the two base DC levels; adjustable $R_2$ sets the voltage between them. $C_1,C_2$ pass the same AC input to $Q_1,Q_2$ without disturbing those DC levels. Cut-off bias gives Class B; a small idle current gives Class AB and removes crossover distortion.

• On the positive half-cycle, $Q_1$ drives power transistor $Q_3$. The upper NPN Darlington pair sources current from $+V_{CC}$ into the internal output node; $Q_2,Q_4$ are off.

• On the negative half-cycle, PNP driver $Q_2$ drives NPN power transistor $Q_4$. The Sziklai pair sinks current from the internal output node to ground; $Q_1,Q_3$ are off.

• The two half-cycles meet at $Q_3\text{ emitter}=Q_2\text{ emitter}=Q_4\text{ collector}$. In this single-supply circuit that node carries a DC bias, so $C_3$ blocks the DC and passes only the amplified AC waveform to $R_L$.

[!NOTE]

Tip — Why use a Sziklai pair here?

It gives high composite current gain while keeping both power devices $Q_3,Q_4$ as rugged NPN transistors. Compared with an NPN Darlington, its effective input-to-output turn-on is roughly one $V_{BE}$ rather than two, and the local feedback tends to lower output impedance and distortion. It still needs correct biasing and thermal compensation; it does not perfectly match the upper Darlington automatically.

Class-B device-current waveforms and reconstructed output.

In Class B operation, each active device conducts for exactly $180^\circ$ of the input cycle.

Note

Derivation — Efficiency $=\pi/4$

Key facts:

• Maximum efficiency $\eta_{\max}=\dfrac{\pi}{4}=78.5\%$ — far better than Class A; also written $\eta_{\max}=25\pi\%$ (since $\tfrac{\pi}{4}\times100=25\pi$).

• Push–pull symmetry gives no even-harmonic distortion; the principal residual is the third harmonic.

• Maximum total device dissipation $=\dfrac{2V_{CC}^{2}}{\pi^{2}R_L}\approx0.4\,P_{ac(\max)}$, occurring at $V_{om}=\dfrac{2V_{CC}}{\pi}\approx0.636\,V_{CC}$ — not at full output.

Derivation: peak current $I_p=V_{om}/R_L$; average supply current (both halves) $=\dfrac{2I_p}{\pi}$, so $P_{dc}=\dfrac{2}{\pi}V_{CC}I_p$ while $P_{ac}=\tfrac12 V_{om}I_p$. At full swing $V_{om}=V_{CC}$:

$$\eta_{\max}=\dfrac{\tfrac 12V_{CC}I_p}{\tfrac{2}{\pi}V_{CC}I_p} =\dfrac{\pi}{4}\approx 78.5\%$$

[!NOTE]

Exam Pitfall — Crossover Distortion — the main drawback

• A BJT needs $V_{BE}\approx0.7$ V before it conducts. Near the zero-crossing, $|v_i|$ is below this threshold, so neither transistor is on.

• This produces a flat “dead zone” in the output every time the signal crosses zero — called crossover distortion.

• Cured by a small forward bias so both devices stay slightly on near zero $\Rightarrow$ this is Class AB.

Class-B crossover distortion caused by the transistor dead zone.

Note

Advantages

• High efficiency (78.5 %) — much better than Class A.

• Very low standby power; devices are cool at idle.

• Push–pull symmetry cancels even harmonics and DC (no transformer core saturation).

• Smaller heat sink than Class A for the same output.

[!NOTE]

Disadvantages

• Crossover distortion (its defining problem).

• Needs two matched (complementary) transistors.

• Complementary form needs a dual supply; transformer form is bulky.

[!NOTE]

Applications

• Audio power output stages (in practice run as Class AB to remove crossover distortion).

• Battery-powered equipment where efficiency is important.

Class AB Amplifier

Note

Key Concept — In one line

A small forward bias keeps both push–pull devices slightly conducting at zero signal, so each conducts for a little more than $180^\circ$ — removing crossover distortion.

[!NOTE]

Working — How it works

• Construction: same push–pull pair as Class B, but a small standing current is set by bias diodes or a $V_{BE}$-multiplier placed between the two bases.

• Working: because a small current flows even at zero input there is no dead zone $\Rightarrow$ no crossover distortion; conduction angle is $>180^\circ$.

• Efficiency: between Class A and Class B — it sacrifices a little efficiency versus B for better linearity, while staying far more efficient than A.

[!NOTE]

Applications

The standard audio output stage; the quasi-complementary AB form is the most common power amplifier.

Transformer-coupled class-AB output stage.

In the transformer-coupled Class AB stage, $R_1,R_2$ establish forward bias and $R_E$ stabilises the quiescent current.

Class-AB device-current waveforms and reconstructed output.

Class AB device current lasts slightly more than $180^\circ$ because a small quiescent current remains at zero input.

Class C Amplifier

Note

Key Concept — In one line

Biased beyond cut-off, the device conducts for less than $180^\circ$ (only a small part of each cycle) — giving very high efficiency (up to 90%) but heavy distortion, so it needs a tuned load.

[!NOTE]

Working — How it works

• Two modes: tuned (an $LC$ tank restores the sine by the flywheel effect) and untuned.

• Working: only a narrow current pulse flows each cycle; the parallel $LC$ tank rings at resonance $f_0=\dfrac{1}{2\pi\sqrt{LC}}$ and rebuilds the wanted sinusoid, filtering out the rest.

• Distortion: very high $\Rightarrow$ not used for audio.

[!NOTE]

Applications

RF and IF power amplifiers, transmitters, oscillators, and frequency multipliers; efficiency $\sim\!90\%$.

Class-C amplifier with a tuned collector load.

In the tuned-mode Class C amplifier, the RFC supplies negative DC base bias while blocking RF, and the parallel $LC$ tank selects the output sinusoid.

Class-C current pulses and tuned-load output waveform.

Class C device current is a narrow pulse with conduction angle less than $180^\circ$.

Class D Amplifier

Note

Key Concept — In one line

The device works as a switch (fully ON/OFF), driven by PWM, so it dissipates almost no power $\Rightarrow$ efficiency $\sim\!90\%$ with no bulky heat sinks or transformers.

[!NOTE]

Working — How it works

• Working: the input is turned into a pulse train by PWM (or pulse-density / sigma–delta modulation); the switches reproduce it at high power; an $LC$ low-pass filter averages the pulses back into the analog waveform.

• Topologies: half-bridge (two active devices) and full-bridge (four active devices).

[!NOTE]

Advantages

Very high efficiency, little heat, and compact — no bulky heat sinks or transformers.

[!NOTE]

Disadvantages

Switching noise / EMI; it needs the output $LC$ filter.

[!NOTE]

Applications

Modern audio amplifiers and motor drives.

Class-D switching-amplifier signal chain.

Class D signal chain: PWM $\to$ switching bridge $\to$ $LC$ filter $\to$ load.

Other switching classes (E, F)

Class E and Class F are switching power amplifiers offering very high efficiency, used at very high frequencies where the switching time is comparable to the duty time.

Power Amplifier Characteristics

Efficiency

$$\eta=\dfrac{P_o}{P_i}\times 100\%$$

$P_o$ = AC power delivered to the load, $P_i$ = DC input power (also called conversion efficiency).

Harmonic Distortion (five-point method)

Device non-linearity adds harmonics, and distortion grows with signal level. From five sampled output-current points ($I_{\max},I_{+1/2},I_Q,I_{-1/2},I_{\min}$) the Fourier amplitudes are:

$$\begin{aligned} A_0 & =\tfrac{1}{6}\!\left(I_{\max}+2I_{+1/2}+2I_{-1/2}+I_{\min}\right)-I_Q, & A_1 & =\tfrac{1}{3}\!\left(I_{\max}+I_{+1/2}-I_{-1/2}-I_{\min}\right), \\ A_2 & =\tfrac{1}{4}\!\left(I_{\max}-2I_Q+I_{\min}\right), & A_3 & =\tfrac{1}{6}\!\left(I_{\max}-2I_{+1/2}+2I_{-1/2}-I_{\min}\right), \\ A_4 & =\tfrac{1}{12}\!\left(I_{\max}-4I_{+1/2}+6I_Q-4I_{-1/2}+I_{\min}\right). \end{aligned}$$

Individual and total harmonic distortion:

$$D_n=\dfrac{A_n}{A_1}\times 100\%\ (n\!=\!2,3,4,\dots),\qquad D=\sqrt{D_2^{2}+D_3^{2}+D_4^{2}+\dots}$$

Fundamental power $P_1=\dfrac{A_1^{2}R_L}{2}$; total output power

$$P=\left(A_1^{2}+A_2^{2}+A_3^{2}+\dots\right)\dfrac{R_L}{2}=(1+D^{2})\,P_1$$

Thermal Management

• Average device dissipation: $P_D=V_{CE}\,I_C$.

• The limiting factor is the maximum collector junction temperature. Above a rated case temperature the allowed $P_D$ derates linearly to zero at the maximum case temperature ($\sim\!200^\circ$C for silicon; Si withstands more than Ge).

• Improve power handling with heat sinks (large metal case area) or thermoelectric (Peltier) coolers — solid-state heat pumps that move heat against the temperature gradient.

Power-transistor dissipation derating with case temperature.

Silicon power-transistor derating curve.

All Classes — Comparison

Class	Conduction	$\eta_{\max}$	Distortion	Typical use
A	$360^\circ$	% / 50%	lowest	preamp, hi-fi small-signal
AB	$>180^\circ$	–78%	low (no crossover)	audio output (common)
B	$180^\circ$	%	crossover	audio push–pull
C	$<180^\circ$	up to 90%	high (needs tank)	RF/IF, transmitters
D	switch (PWM)	$\sim\!90\%$	low (filtered)	audio, motor drive
E,F	switching	very high	—	very-high-frequency

Note

Tip

Efficiency order $A<AB<B<C<D$. A = All the cycle (linear, lossy, hottest at idle); B = Both halves shared (crossover); AB = the audio fix; C = Communications/RF (tuned, $<$ half); D = Digital-style switching.

Feedback Amplifiers

Feedback returns a fraction of an amplifier output to its input. Negative (degenerative) feedback subtracts the returned signal from the source and is used to control linear-amplifier behavior. Positive (regenerative) feedback reinforces the source and is used deliberately in oscillators, hysteresis and switching; excessive positive feedback makes a linear stage unstable.

Native negative-feedback block diagram with an explicit subtracting input. Changing the lower sign changes the algebra to positive feedback.

Closed-loop gain and desensitivity

With the sign in the figure,

$$x_e=x_s-\beta x_o,\qquad x_o=Ax_e.$$

Therefore

$$\begin{aligned} x_o&=A(x_s-\beta x_o),\nonumber\\ x_o(1+A\beta)&=Ax_s,\nonumber\\ \boxed{A_f(s)=\frac{x_o}{x_s} =\frac{A(s)}{1+A(s)\beta(s)}}. \end{aligned}$$

The generally complex, frequency-dependent product

$$L(s)=A(s)\beta(s)$$

is the loop gain; $1+L$ is the return difference. When $|L|\gg1$ and the loop phase still represents negative feedback, $A_f\simeq1/\beta$. For positive feedback under the same algebraic convention,

$$\boxed{A_{f,+}=\frac{A}{1-A\beta}},$$

so the two denominators must not be interchanged.

For scalar $A$ and fixed $\beta$, logarithmic differentiation gives

Caution

Key Formula — Gain Sensitivity

$$\boxed{\frac{dA_f/A_f}{dA/A}=\frac{1}{1+A\beta}}.$$

Thus sufficiently large negative loop gain makes closed-loop gain less sensitive to transistor gain, temperature and supply variation. This is a local, in-band result because loop-gain magnitude and phase vary with frequency.

Qualified effects of negative feedback

Property	Effect in the useful negative-feedback band
Gain	Reduced by the return difference $1+L$, but made more predictable; high loop gain exchanges excess open-loop gain for accuracy.
Bandwidth	For a stable single-dominant-pole stage and nearly constant $\beta$, $f_{Hf}\simeq f_H(1+L_0)$ and $f_{Lf}\simeq f_L/(1+L_0)$, so gain-bandwidth product is approximately conserved. These are not multipole identities.
Distortion	Nonlinear products generated inside the effective forward-path loop are reduced approximately by $1+
Noise	Some noise generated inside the enclosed forward path is reduced at the output relative to signal. Source noise and feedback-network thermal noise are not automatically reduced, and a wider noise bandwidth may increase total noise.
Stability and transient response	Parameter stability improves, but accumulated phase lag can make the returned signal regenerative. Inadequate phase margin produces ringing or oscillation, so loop stability must be checked separately.
Impedance	Determined by input mixing and output sampling: there is no single rule that both impedances always rise or always fall.

What negative feedback changes, and the necessary qualification.

Four feedback topologies

Topology is decoded by two independent questions:

1. Is feedback mixed with the input in series as a voltage, or in shunt as a current?

2. Is output voltage sampled across the port (shunt sampling), or output current sampled through the port (series sampling)?

Native topology decoder. The input symbol distinguishes series voltage from shunt current mixing; the output branch distinguishes voltage from current sampling.

Let $D=1+A\beta$ in a frequency band where feedback is negative and $D$ may be treated as a positive scalar magnitude. The impedance rules and stabilised gain quantities are:

Topology	Amplifier quantity	Sample–mix	$Z_{in,f}$	$Z_{out,f}$
Voltage-series	$A_v=V_o/V_s$	Voltage–series (shunt–series)	$DZ_{in}$	$Z_{out}/D$
Voltage-shunt	$R_m=V_o/I_s$	Voltage–shunt (shunt–shunt)	$Z_{in}/D$	$Z_{out}/D$
Current-series	$G_m=I_o/V_s$	Current–series (series–series)	$DZ_{in}$	$DZ_{out}$
Current-shunt	$A_i=I_o/I_s$	Current–shunt (series–shunt)	$Z_{in}/D$	$DZ_{out}$

Feedback topology, gain quantity and impedance effects.

The memory rule follows directly: series input raises $Z_{in}$; shunt input lowers it; voltage sampling lowers $Z_{out}$; current sampling raises it. Series mixing makes the source overcome a feedback voltage, while shunt mixing adds a current path. Voltage sampling tends toward a stiff voltage source and current sampling toward a stiff current source.

Advantages of negative feedback are accurate gain, useful impedance control, wider bandwidth in common dominant-pole designs, and reduced enclosed distortion and some internal noise. Its costs are reduced gain, extra network noise/loading and the possibility of ringing or oscillation. Applications include op-amps, audio and instrumentation amplifiers, active filters, regulators and communication signal paths.

Differential Amplifiers

A differential amplifier is a direct-coupled two-input stage that amplifies the difference between its inputs while rejecting a signal common to both. It is the usual input stage of an op-amp and a basic interface for balanced sensors and communication lines.

Define the input quantities before deriving a gain:

$$v_{id}=v_1-v_2,\qquad v_{cm}=\frac{v_1+v_2}{2},$$

so that

$$v_1=v_{cm}+\frac{v_{id}}{2},\qquad v_2=v_{cm}-\frac{v_{id}}{2}.$$

Native matched BJT differential pair with equal collector loads and a constant-current tail. Either collector or their difference may be output.

At balance, $v_1=v_2$, matched devices divide $I_T$ equally, collector drops are equal and $v_{od}=0$ ideally. For positive $v_{id}$, $Q_1$ current rises and $v_{c1}$ falls; $Q_2$ current falls and $v_{c2}$ rises. The pair therefore steers an almost constant tail current between its branches.

For common-mode drive $v_1=v_2=v_{cm}$, both branch currents try to move in the same direction. The tail element then develops degenerative emitter voltage. A high small-signal tail resistance strongly opposes total-current change. Matched collector changes cancel in an ideal double-ended output, while a single-ended output and practical mismatch leave finite common-mode gain.

Differential and common-mode half-circuits

Native half-circuit views for a resistor-tail pair. An active tail replaces $R_E$ by a much larger incremental resistance.

Differential gain, common-mode gain and CMRR

Assume matched devices and loads, large $\beta$, large transistor $r_o$, and

$$r_e\simeq\frac{V_T}{I_E}\simeq\frac{26\,\text{mV}}{I_E}$$

at room temperature. With $v_1=+v_{id}/2$ and $v_2=-v_{id}/2$,

$$\Delta i_{c1}\simeq\frac{v_{id}}{2r_e},\qquad \Delta i_{c2}\simeq-\frac{v_{id}}{2r_e}.$$

Consequently,

$$v_{c1}=-\frac{R_C}{2r_e}v_{id},\qquad v_{c2}=+\frac{R_C}{2r_e}v_{id}.$$

For the output polarities shown in the figure,

Caution

Key Formula — Differential-Pair Gains

$$\boxed{A_{d,se}=\frac{v_{c1}}{v_{id}} \simeq-\frac{R_C}{2r_e}},\qquad \boxed{A_{d,de}=\frac{v_{c2}-v_{c1}}{v_{id}} \simeq\frac{R_C}{r_e}}.$$

With a shared resistor $R_E$ and a single-collector output,

$$A_{c,se}\simeq-\frac{R_C}{r_e+2R_E} \simeq-\frac{R_C}{2R_E}\quad(R_E\gg r_e).$$

The common-mode rejection ratio must compare gains measured at the same output:

Caution

Key Formula — Common-Mode Rejection Ratio

$$\boxed{\mathrm{CMRR}=\left|\frac{A_d}{A_c}\right|},\qquad \boxed{\mathrm{CMRR}_{dB}=20\log_{10}\mathrm{CMRR}}.$$

For the single-ended gains above,

$$\boxed{\mathrm{CMRR}_{se}\simeq\frac{R_E}{r_e}}.$$

An ideal matched double-ended output has $A_{c,de}=0$ and hence infinite ideal CMRR; mismatch makes it finite.

[!NOTE]

Law — The Common CMRR Convention Trap

Some elementary treatments combine the double-ended differential gain $R_C/r_e$ with the single-ended common-mode magnitude $R_C/(2R_E)$ and quote $2R_E/r_e$. That is a useful textbook proxy only when the convention is explicitly prescribed; it compares two different output definitions. A rigorous CMRR uses one physical output for both gains. State whether the output is single-ended or double-ended before quoting a result.

[!NOTE]

Example — Differential Gain and CMRR

A matched pair has $R_C=4.7\,\text{k}\Omega$, tail current $I_T=2\,\text{mA}$ and a shared tail resistor $R_E=100\,\text{k}\Omega$. Neglect $r_o$ and assume equal current division. Then

$$I_E\simeq1\,\text{mA},\qquad r_e\simeq\frac{26\,\text{mV}}{1\,\text{mA}}=26\,\Omega.$$

For one collector,

$$\begin{aligned} A_{d,se}&=-\frac{4700}{2(26)}=-90.4,\\ A_{c,se}&=-\frac{4700}{26+2(100000)}=-0.0235,\\ \mathrm{CMRR}_{se}&=\left|\frac{-90.4}{-0.0235}\right| \simeq3846,\\ \mathrm{CMRR}_{dB}&=20\log_{10}(3846)=71.7\,\text{dB}. \end{aligned}$$

The double-ended differential gain is about $181$, while its ideal common-mode gain is zero only for exact symmetry.

Active tails and practical errors

A large resistor improves CMRR but consumes excessive DC voltage. A transistor current sink supplies the required DC current while presenting high small-signal output resistance. For a Zener-referenced sink,

$$\boxed{I_T\simeq\frac{V_Z-V_{BE}}{R_S}}.$$

A current mirror uses a diode-connected reference transistor to establish $V_{BE}$ and a matched output transistor to sink approximately the same current. In a representative dual-supply arrangement,

$$I_{ref}\simeq\frac{V_{CC}+|V_{EE}|-V_{BE}}{R},\qquad I_T\simeq I_{ref}.$$

Finite $\beta$, Early effect, device mismatch, temperature difference and compliance voltage limit accuracy. Zener noise and drift are additional limits of the Zener source.

Tail	DC setting	Incremental resistance/CMRR	Main limitation
Resistor	Supply and $R_E$	Moderate; rises only with physical resistance	Large resistance needs large voltage
Zener sink	$V_Z$, $V_{BE}$ and $R_S$	High; low common-mode gain	Zener noise, drift and compliance
Current mirror	Reference branch and matching	High; compact and IC-friendly	Mismatch, finite $\beta$, Early effect and compliance

Tail-network comparison for a differential pair.

Practical limitations include input offset from device/load mismatch, input bias and offset currents

$$I_B=\frac{I_{B1}+I_{B2}}{2},\qquad I_{OS}=|I_{B1}-I_{B2}|,$$

finite common-mode input range, tail-source compliance and collector saturation headroom. Large $v_{id}$ steers almost all tail current to one branch and violates the small-signal model. Matched devices, symmetric layout, equal source resistances and trimming reduce error. High CMRR rejects common hum, balanced-line pickup, sensor-lead interference and ground-potential variation.

Cascode Amplifiers

A cascode is one composite stage formed by stacking a transconductance input device below a current-buffer device: CE followed by CB for BJTs, or CS followed by CG for FETs. The upper device keeps the lower device’s collector or drain at nearly constant AC voltage while transferring signal current to a high-resistance output node.

Native CE–CB and CS–CG cascodes. The upper device shields the input device from the large output-voltage swing.

In the BJT form, $Q_1$ converts $v_i$ into collector-current variation. The emitter of common-base $Q_2$ presents low incremental resistance, so the $Q_1$ collector voltage changes little. $Q_2$ conveys the current to $R_C$, which produces an amplified inverted output. In the MOS form, common-gate $M_2$ similarly holds the $M_1$ drain nearly fixed and transfers its drain current to $R_D$.

Miller suppression, gain and port resistances

For an ordinary inverting stage, a feedback capacitance appears at its input as $C_f(1-A_v)$. In a cascode, the relevant local gain from the lower device input to its collector/drain is small. The voltage across $C_{bc1}$ or $C_{gd1}$ therefore changes little, greatly reducing Miller multiplication. The result is lower effective input capacitance, higher upper cutoff and better reverse isolation. Output-node capacitance can still form a limiting pole.

The lower device supplies transconductance and the upper device supplies isolation and high intrinsic output resistance. A useful loaded estimate is

Caution

Key Formula — Cascode Gain and Output Resistance

$$\boxed{A_v\simeq-g_{m1} \left(R_{load}\parallel r_{o,cas}\right)}.$$

For two comparable devices with $g_mr_o\gg1$,

$$\boxed{r_{o,cas}\simeq r_{o1}+r_{o2}+g_{m2}r_{o1}r_{o2} \simeq g_mr_o^2}.$$

The external $R_C$, $R_D$, active load and following stage usually reduce the actual output resistance and gain.

For a BJT cascode, $R_{in}\simeq r_{\pi1}$ in parallel with its bias network. For a MOS cascode, gate input resistance is ideally very high and is limited by bias resistance and leakage. Looking into the lower device’s collector/drain, the upper CB/CG device presents a low resistance of order $1/g_{m2}$; looking into the final output, the cascode resistance is high as shown above.

Advantages are low Miller effect, wide bandwidth, high reverse isolation, high output resistance and potentially high gain. Costs are extra device and bias circuitry, greater voltage headroom, reduced low-supply output swing, added noise and a possible high-impedance output pole. Applications include RF and IF amplifiers, low-noise and wideband front ends, oscilloscope inputs, op-amp gain stages, active loads and high-output-resistance current mirrors.

Differential pair versus cascode

Feature	Differential pair	Cascode
Primary purpose	Amplify $v_1-v_2$ and reject common mode	Suppress Miller feedback, isolate ports and raise output resistance
Input structure	Two signal inputs sharing one tail current	One principal signal input; upper device receives fixed bias
Signal mechanism	Steers tail current between two branches	Transfers one device’s signal current through a CB/CG buffer
Key figure of merit	Differential gain, common-mode gain and CMRR	Bandwidth, reverse isolation, gain and output resistance
Headroom	Tail source and both input devices need compliance	Stacked devices need extra voltage and reduce output swing
Typical use	Op-amp/instrumentation and balanced-input front end	RF, wideband, high-gain or high-output-resistance stage

Differential and cascode amplifiers solve different problems.

A cascode must also be distinguished from an ordinary cascade. In a cascode, devices share one current path and the intermediate voltage swing is intentionally small. In a cascade, the output of one complete stage drives another and stage gains multiply; each inverting stage may retain its own Miller limitation.

Supplementary Amplifier Topics

The following topics provide complementary derivations, circuit interpretations, comparison tables and worked design checks for differential, operational and feedback amplifiers.

Differential Amplifiers

A differential amplifier is a direct-coupled, two-input stage that amplifies the input difference while rejecting a signal common to both inputs. For the polarity $v_{id}=v_1-v_2$,

$$v_o=A_d(v_1-v_2)=A_dv_{id}.$$

It is the standard input stage of op-amps and instrumentation amplifiers.

It is useful to separate any pair of input voltages into differential and common-mode components:

$$v_{id}=v_1-v_2,\qquad v_{cm}=\frac{v_1+v_2}{2},\qquad v_{1,2}=v_{cm}\pm\frac{v_{id}}{2}.$$

Matched BJT differential amplifier with equal collector loads and a shared resistor tail. A current-source or current-mirror tail is preferred in practical high-CMRR stages.

At balance, matched transistors divide the tail current equally and their collector voltages are equal. A positive $v_{id}$ steers current toward $Q_1$: $v_{c1}$ falls while $v_{c2}$ rises. Common-mode drive attempts to change both currents together; the shared tail impedance develops degenerative feedback and opposes that change.

At room temperature, with large transistor $\beta$ and negligible $r_o$,

$$r_e'\simeq\frac{V_T}{I_E}\simeq\frac{26\,\mathrm{mV}}{I_E}.$$

For equal collector resistors and the indicated output polarities,

Caution

Key Formula — Differential and common-mode gains

$$\boxed{A_{d,se}\simeq-\frac{R_C}{2r_e'}},\qquad \boxed{A_{d,de}\simeq\frac{R_C}{r_e'}},$$$$\boxed{\frac{v_{c1}}{v_{id}}\simeq-\frac{R_C}{2r_e'}},\qquad \boxed{\frac{v_{c2}}{v_{id}}\simeq+\frac{R_C}{2r_e'}},\qquad \boxed{\frac{v_{c2}-v_{c1}}{v_{id}}\simeq\frac{R_C}{r_e'}}.$$$$\boxed{A_{c,se}\simeq-\frac{R_C}{r_e'+2R_E} \simeq-\frac{R_C}{2R_E}}\qquad(R_E\gg r_e').$$

The common-mode rejection ratio is

$$\boxed{\mathrm{CMRR}=\left|\frac{A_d}{A_c}\right|},\qquad \boxed{\mathrm{CMRR}_{\mathrm{dB}}=20\log_{10}\mathrm{CMRR}}.$$

For the same single-ended collector output,

$$\mathrm{CMRR}_{se}\simeq\frac{R_E}{r_e'}.$$

With matched devices and equal collector resistors, the double-ended common-mode gain is ideally zero ($A_{c,de}\to 0$), so rigorous CMRR comparison should keep output convention explicit.

Note

Law — State the CMRR output convention

The often-quoted textbook result $2R_E/r_e'$ combines the double-ended gain $R_C/r_e'$ with the single-ended common-mode approximation $R_C/(2R_E)$. It is acceptable only when that convention is explicitly prescribed. A physical CMRR compares differential and common-mode gains at the same output. An ideal matched double-ended output has zero common-mode gain; mismatch makes the practical value finite.

[!NOTE]

Key Point — Why the tail resistor becomes a current source

Increasing $R_E$ raises the tail’s small-signal resistance and lowers $|A_c|$, but a very large resistor needs excessive DC voltage. A current sink or current mirror supplies the required bias current while presenting a high incremental resistance, thereby improving CMRR without the same voltage loss. An ideal current-source tail has infinite small-signal resistance and zero ideal common-mode gain.

Operational Amplifiers

An operational amplifier (op-amp) is a very-high-gain, DC-coupled, differential voltage amplifier. In linear open-loop operation,

$$v_o=A_{OL}(v_+-v_-)=A_{OL}v_d,$$

where $A_{OL}$ is the open-loop differential gain and $v_d=v_+-v_-$. This relation is valid only while the output remains in the unsaturated range.

Direct coupling allows response down to $0\,\mathrm{Hz}$, but it also means input offset and drift appear at the output after gain. The op-amp symbol, power pins and internal stage concept are shown below.

Powered op-amp symbol and a conceptual internally compensated three-stage signal path with explicit supply distribution.

Practical and Ideal Models

At low frequency, a practical op-amp can be modeled by finite differential input resistance $R_i$, a dependent source $A_{OL}v_d$, and non-zero output resistance $R_o$. The ideal model is the limiting case

$$A_{OL}\to\infty,\qquad R_i\to\infty,\qquad R_o\to0.$$

Practical and ideal op-amp terminal models. The finite-gain VCVS is ground referenced and followed by series $R_o$; the ideal limit has $A_{OL}\to\infty$, $R_i\to\infty$, and $R_o\to0$.

Parameter	Ideal	Practical trend	Consequence
Open-loop gain $A_{OL}$	$\infty$	$10^4$ to $10^6$ (device dependent)	Closed-loop gain has finite-gain error.
Input resistance $R_i$	$\infty$	$10^5\,\Omega$ to $10^{12}\,\Omega$	Input currents are small, not exactly zero.
Output resistance $R_o$	$0$	typically ohms to tens of ohms	Load changes cause finite output drop.
Bandwidth / GBW	$\infty$	finite, compensation dependent	Gain and phase vary with frequency.
Slew rate	$\infty$	finite ($\sim0.5\,\mathrm{V/\mu s}$ to hundreds of $\mathrm{V/\mu s}$)	Large-signal slope limit can distort waveforms.
Offsets and drift	$0$	finite, temperature/time dependent	DC accuracy needs offset/drift budgeting.

Ideal assumptions and practical interpretation (order-of-magnitude only).

Note

Key Point — Ideal op-amp rules under negative feedback

For negative feedback with unsaturated output and large loop gain,

$$i_+\approx i_-\approx0,\qquad v_+\approx v_-.$$

These are consequences of high but finite gain, not universal laws. They can fail in open-loop comparator use, positive feedback, startup transients, or output saturation.

Frequency Response, Loop Gain and Closed-Loop Accuracy

A compensated op-amp is often approximated by a dominant-pole model:

$$A_{OL}(s)\approx\frac{A_0}{1+s/\omega_p}.$$

Beyond the pole, the open-loop magnitude falls at about $20\,\mathrm{dB/dec}$ until higher poles appear. In the one-pole region,

$$\mathrm{GBW}\approx A_0f_p\approx f_T$$

is an approximation, where $f_T$ is the unity-gain frequency.

Exact magnitudes for the one-pole model with $A_0=10^5$ ($100\,\mathrm{dB}$), $f_p=10\,\mathrm{Hz}$, and $f_T\approx1\,\mathrm{MHz}$. Closed-loop bandwidth follows the gain–bandwidth product to the accuracy of this model.

For a standard negative-feedback amplifier with feedback factor $\beta$,

Caution

Key Formula — Loop gain and closed-loop gain

$$\boxed{T=A_{OL}\beta},\qquad \boxed{A_{CL}=\frac{A_{OL}}{1+A_{OL}\beta}}.$$

Therefore,

$$\frac{A_{OL}}{A_{CL}}=1+T.$$

Relative to the ideal closed-loop value $A_{ideal}=1/\beta$, the fractional gain error magnitude is

$$\left|\frac{A_{ideal}-A_{CL}}{A_{ideal}}\right|\approx\frac{1}{|T|} \quad (|T|\gg1).$$

Slew Rate, Full-Power Bandwidth and Settling

Slew-rate measurement with a voltage-follower step test. The large-signal output needs $\Delta t=\Delta V/SR$ to traverse the step.

Caution

Key Formula — Slew-limited sine condition

$$SR=\max\left|\frac{\mathrm{d}v_o}{\mathrm{d}t}\right|, \qquad f_{FP}=\frac{SR}{2\pi V_p}=\frac{SR}{\pi V_{pp}}.$$

In internally compensated op-amps, slew-rate limiting is set by finite internal current charging/discharging the compensation capacitor:

$$\boxed{SR\approx\frac{I_{\max}}{C_c}}.$$

If required output slope exceeds $SR$, distortion occurs even when small-signal bandwidth seems adequate.

For a step response with final value $v_o(\infty)$ and step size $\Delta v_o$, settling time to error band $\varepsilon$ is formally defined as

$$t_s(\varepsilon)=\min\Big\{t:\ |v_o(t')-v_o(\infty)|\le\varepsilon|\Delta v_o|, \ \forall t'\ge t\Big\}.$$

Typical data-sheet bands are $\varepsilon=0.001$ (0.1%) or $\varepsilon=0.0001$ (0.01%). Practical settling depends on step amplitude, slew interval, small-signal poles/zeros, phase margin and load.

CMRR, PSRR, Offsets and Drift

Caution

Key Formula — Common-mode rejection ratio

$$\boxed{\mathrm{CMRR}=\left|\frac{A_d}{A_c}\right|}, \qquad \boxed{\mathrm{CMRR}_{\mathrm{dB}}=20\log_{10}\left|\frac{A_d}{A_c}\right|}.$$

CMRR is meaningful only for valid common-mode input range and linear output range. Practical CMRR changes with frequency and source imbalance.

PSRR is often specified through input-referred offset sensitivity, $\Delta V_{OS}/\Delta V_S$ (smaller is better). Some data sheets use the reciprocal ratio in dB. Regardless of convention, stronger supply rejection is better and is frequency dependent.

Input offset voltage $V_{OS}$ is the differential DC voltage needed to force $\,v_o=0$. Offset drift is its change with temperature/time. Broadly, general parts may sit around millivolts, while precision parts can be in the microvolt range.

Op-Amp Categories and Application-Specific Forms

Category	Emphasis	Typical trade-off or caution
General-purpose	Balanced cost, gain, speed, input performance	Does not maximize any single metric.
High-speed	High GBW, high SR, fast settling	Layout sensitivity, power and noise penalties.
Precision	Very low $V_{OS}$, drift, bias errors; high DC accuracy	Often lower speed and higher cost.
Power	High output current/voltage, protection features	Thermal design and stability with reactive loads.
Comparator (dedicated)	Fast open-loop switching to logic states	Not interchangeable with linear op-amp behavior.

Common op-amp categories (ranges are broad and device dependent).

Note

Key Point — Comparator versus op-amp in open loop

Using an ordinary op-amp as a comparator can work in some cases but may suffer slow saturation recovery, invalid input common-mode operation, or unsuitable output levels. Dedicated comparators are designed for switching behavior.

Instrumentation Amplifier (Three-Op-Amp Topology)

An instrumentation amplifier is a circuit category, not merely one op-amp type. It combines very high input impedance, accurate differential gain and strong common-mode rejection.

Three-op-amp instrumentation amplifier. $R_G$ sets the first-stage differential gain without loading either input, and matched subtractor ratios reject the first-stage common-mode component.

If the difference-stage resistor ratios are matched $R_3/R_2=R_5/R_4$, then

Caution

Key Formula — Three-op-amp instrumentation-amplifier gain

$$\boxed{v_o=\left(1+\frac{2R_1}{R_G}\right)\frac{R_3}{R_2}(v_2-v_1)}.$$

Single-resistor gain setting by $R_G$ is a major practical advantage in precision sensor interfaces.

Isolation Amplifier

Isolation-amplifier signal path with two electrically independent ground domains. The dashed arrow denotes encoded information transfer, not a conductive connection across the barrier.

An isolation amplifier transfers the measurement signal across a galvanic barrier so that input and output grounds remain electrically separated for safety and ground-loop control. Coupling across the barrier is commonly transformer, optical, or capacitive. Specifications include isolation voltage, leakage, CMRR versus frequency, and linearity.

Feedback in Amplifiers

A feedback amplifier returns a controlled fraction of output to the input summing mechanism. Let $x_s$ be source signal, $x_i$ be the internal error (driving) signal, $x_o$ be output, and $x_f=\beta x_o$ be feedback.

General negative-feedback loop with source signal $x_s$, error signal $x_i$, output $x_o$, and feedback $x_f$.

With a real-positive sign convention:

$$\text{negative feedback: }x_i=x_s-\beta x_o, \qquad \text{positive feedback: }x_i=x_s+\beta x_o.$$

If forward gain is $A=x_o/x_i$, then

$$A_f\equiv\frac{x_o}{x_s}=\frac{A}{1+A\beta}\quad\text{(negative-feedback sign convention)}$$

and for regenerative form

$$A_f=\frac{A}{1-A\beta}.$$

Note

Law — Sign and phase convention

Do not classify feedback only from $|1+A\beta|$ being greater or less than one. The correct classification comes from the summing polarity and loop phase. In frequency-domain systems, a nominally negative-feedback connection can become regenerative at frequencies where loop phase shift drives $1+L(j\omega)$ toward zero.

Define loop gain $L(s)=A(s)\beta(s)$ and desensitivity factor

$$D(s)=1+L(s).$$

In the useful negative-feedback band, $D$ is typically large and positive in its real part, but in general it is complex and frequency dependent.

Barkhausen Condition and Stability Meaning

Under the above denominator convention, the linear oscillation boundary is

$$1+L(j\omega_0)=0$$

which is equivalent to

$$|L(j\omega_0)|=1, \qquad \angle L(j\omega_0)=(2k+1)\pi.$$

This is a condition for marginal linear oscillation. It is not proof of physically infinite output; practical oscillators settle by nonlinear amplitude limiting.

Desensitivity, Gain Stability and Sensitivity

For $\beta$ treated as constant with respect to plant variation,

$$A_f=\frac{A}{1+A\beta}$$

leads to

$$\frac{\mathrm{d}A_f}{A_f}=\frac{1}{1+A\beta}\,\frac{\mathrm{d}A}{A}.$$

Hence sensitivity of closed-loop gain to open-loop gain is

$$S_A^{A_f}=\frac{\partial \ln A_f}{\partial \ln A}=\frac{1}{1+A\beta}=\frac{1}{D}.$$

For high loop gain ($|A\beta|\gg 1$ in the intended band),

$$A_f\approx\frac{1}{\beta},$$

so closed-loop gain is mainly set by the feedback network.

Bandwidth and Frequency-Response Trade-Off

For a dominant-pole or approximately constant loop-gain region, negative feedback widens useful bandwidth roughly by $D$ while reducing midband magnitude by a similar factor:

$$BW_f\approx D\,BW, \qquad f_{Lf}\approx\frac{f_L}{D}, \qquad f_{Hf}\approx D\,f_H.$$

These are one-pole approximations, not universal equalities. As loop gain is pushed upward, phase margin and stability must be rechecked.

Distortion and Noise Caveats

If nonlinear distortion or internally generated noise is injected inside the high-loop-gain region, its output contribution is reduced approximately by $1/D$:

$$\text{distortion}_f\approx\frac{\text{distortion}}{D}, \qquad N_f\approx\frac{N_{\text{internal}}}{D}.$$

But feedback does not magically remove source/input noise or thermal noise from the feedback network itself, and wider closed-loop bandwidth can increase total integrated output noise.

Four Feedback Topologies

Naming is used in two ways:

• Functional order: sample-mix (voltage/current sample at output, then series/shunt mixing at input).

• Connection order: input-output, often written series-shunt, shunt-shunt, series-series, shunt-series.

Map carefully between them to avoid label reversal.

The four feedback topologies. Voltage sampling measures across the load; current sampling uses a series sense resistor $R_s$ carrying the load current. Dashed arrows represent measured information, while solid arrows show the forward and feedback signal paths.

Functional name	Connection name	Transfer type	$R_{if}$	$R_{of}$	Core closed-loop form
Voltage-series	Series-shunt	Voltage gain $A_V$	$R_iD$	$R_o/D$	$A_{Vf}=\dfrac{A_V}{1+\beta A_V}$
Voltage-shunt	Shunt-shunt	Transresistance $R_M$	$R_i/D$	$R_o/D$	$R_{Mf}=\dfrac{R_M}{1+\beta R_M}$
Current-series	Series-series	Transconductance $G_M$	$R_iD$	$R_oD$	$G_{Mf}=\dfrac{G_M}{1+\beta G_M}$
Current-shunt	Shunt-series	Current gain $A_I$	$R_i/D$	$R_oD$	$A_{If}=\dfrac{A_I}{1+\beta A_I}$

Feedback topology matrix using $D=1+A\beta$ in the intended negative-feedback band.

Loaded/Open-Circuit/Short-Circuit Gain Notes

Use the appropriate open-loop transfer for each topology before applying $A_f=A/(1+A\beta)$.

• Voltage-series: loaded $A_V=v_o/v_i$; if needed, $A_V=A_v\,\dfrac{R_L}{R_o+R_L}$ with open-circuit gain $A_v$.

• Voltage-shunt: loaded transresistance $R_M=v_o/i_i$; often $R_M=R_m\,\dfrac{R_L}{R_o+R_L}$ with open-circuit transresistance $R_m$.

• Current-series: loaded transconductance $G_M=i_o/v_i$; common model $G_M=G_m\,\dfrac{R_o}{R_o+R_L}$ where $G_m$ is short-circuit transconductance.

• Current-shunt: current gain $A_I=i_o/i_i$ from the loaded current model.

These loaded relations are model-dependent approximations; keep open-circuit and short-circuit definitions distinct in derivations.

Typical Realizations

• Voltage-series: emitter follower, source follower, non-inverting op-amp.

• Voltage-shunt: collector-to-base resistor feedback CE stage, inverting op-amp.

• Current-series: CE/CS with unbypassed emitter/source resistor.

• Current-shunt: current-amplifier forms using series output current sensing and shunt current mixing.

Classical voltage-shunt (shunt-shunt) realizations: a CE stage with collector-to-base resistor feedback and the op-amp inverting amplifier.

Practical Topology Identification (Robust Method)

Quick short/open tests are easy to misuse. Prefer structural inspection first:

• Output sample network connected across output node/load implies voltage (shunt) sampling.

• Output sample element inserted in load path implies current (series) sampling.

• Feedback signal inserted in series with source/input loop implies series mixing.

• Feedback current returning to the same summing input node implies shunt mixing.

A circuit-zeroing test can be used only with topology-aware assumptions about controlled sources and loading.