CMOS (Complementary Metal-Oxide-Semiconductor) Devices

Definition and Structure

• Definition: CMOS technology integrates both P-type and N-type enhancement-mode MOSFETs on the same silicon substrate. The two devices operate in a complementary manner to perform logic operations.

• Basic component: The foundational CMOS logic block is the CMOS inverter, which uses one P-channel MOSFET ($Q_2$) and one N-channel MOSFET ($Q_1$) connected in series between the supply rails.

• Terminal connections:

  • Gates: The gates are tied together to form the input terminal $V_{in}$, so one input signal controls both transistors simultaneously.

  • Drains: The drains are connected together to form the output terminal $V_{out}$, where the inverted logic signal appears.

  • Sources: The P-channel source connects to the positive supply $V_{SS}$, while the N-channel source connects directly to circuit ground.

Color-coded CMOS inverter and its complementary switching states.

Note

Notation Note

This page follows the supplied diagram and labels the positive supply as $V_{SS}$. Many CMOS texts instead use $V_{DD}$ for the positive rail and $V_{SS}$ for ground; the inverter operation is unchanged.

The physical cross-section shows why CMOS is called complementary. The pMOS device $Q_2$ is formed directly in the N-type substrate, while the nMOS device $Q_1$ is formed inside a P-type well. The substrate contact is tied to the pMOS source at $V_{SS}$, and the P-well contact is tied to the nMOS source at ground. These body connections keep the source-body junctions from becoming forward biased during normal operation.

Integrated CMOS inverter cross-section showing the N-type substrate, P-type well, source and drain diffusions, oxide, gates, contacts, and interconnections.

Features and Advantages (With Technical Reasons)

High Input Impedance

• Why: Each gate is physically isolated from its channel by a non-conductive silicon-dioxide layer ($\mathrm{SiO_2}$), which blocks steady DC gate current. The input behaves mainly as a capacitance.

• Application benefit: Negligible DC loading prevents signal loss and permits high fan-out: one logic gate can drive many following CMOS gates. In practice, a larger fan-out increases total input capacitance and therefore slows transitions.

Exceptionally Low Power Consumption

• Why: In either stable logic state, one transistor is ON and the other is OFF. Ideally, the OFF device breaks the direct path from the supply to ground, so essentially no steady-state current flows through the inverter.

• Application benefit: Low static power makes CMOS highly efficient for battery-powered devices such as smartphones, laptops, digital watches, and embedded systems.

Compact Size (Occupies Less Space Than BJTs)

• Why: MOSFETs have a comparatively simple planar structure and CMOS logic does not require the bulky, continuously dissipating bias resistors used by many BJT logic circuits.

• Application benefit: CMOS supports ultra-high-density integration, allowing billions of transistors to be fabricated on a single microprocessor or memory chip.

Technical Limitations

Switching Delay

• Why: MOSFET gates and interconnections possess inherent capacitance. This capacitance must be charged or discharged whenever the logic state changes, and the available transistor current is finite.

• Impact: Propagation delay increases with load capacitance and fan-out. Traditional CMOS can therefore be slower than some current-driven bipolar logic families in demanding high-frequency applications.

Note

Important Qualification

“CMOS is slower than BJT logic” is a historical comparison, not a universal rule. Modern scaled CMOS is extremely fast and dominates most digital integrated circuits; actual speed depends on device geometry, supply voltage, process, load, and the bipolar logic family used for comparison.

Working Principle (CMOS Inverter Operation)

An inverter acts as a logical NOT gate, converting a HIGH input into a LOW output and a LOW input into a HIGH output.

Case 1: $V_{in}$ Is Logic LOW ($0\,\mathrm{V}$)

• P-channel $Q_2$: Since $V_{GS2}=V_G-V_S=0-V_{SS}=-V_{SS}$, the pMOS turns ON and provides a low-resistance pull-up path to the supply.

• N-channel $Q_1$: Since $V_{GS1}=0\,\mathrm{V}$, the nMOS remains OFF and blocks the pull-down path to ground.

• Output $V_{out}$: The pull-up transistor supplies current to the load and charges the output capacitance, raising $V_{out}$ to approximately $V_{SS}$, which is logic HIGH. Once an unloaded ideal output is fully charged, its steady-state current becomes zero.

Case 2: $V_{in}$ Is Logic HIGH ($V_{SS}$)

• P-channel $Q_2$: Since $V_{GS2}=V_{SS}-V_{SS}=0\,\mathrm{V}$, the pMOS turns OFF and isolates the output from the positive supply.

• N-channel $Q_1$: Since $V_{GS1}=V_{SS}-0=V_{SS}$, the nMOS turns ON and provides a low-resistance pull-down path to ground.

• Output $V_{out}$: The output capacitance and any load discharge through $Q_1$, pulling $V_{out}$ down to approximately $0\,\mathrm{V}$, which is logic LOW.

Input $V_{in}$	pMOS $Q_2$	nMOS $Q_1$	Output $V_{out}$
LOW ($0$)	ON	OFF	HIGH ($V_{SS}$)
HIGH ($V_{SS}$)	OFF	ON	LOW ($0$)

Thus, in Boolean notation,

$$\boxed{V_{out}=\overline{V_{in}}}.$$

Exam Concept: Static vs. Dynamic Power Dissipation

Static Condition

In either stable state, one of the complementary MOSFETs is OFF. The ideal path between $V_{SS}$ and ground is therefore broken, so ideal static power dissipation is zero. A real CMOS inverter has small subthreshold, gate-oxide, and reverse-junction leakage currents, giving

$$P_{static}=V_{SS}I_{leak}.$$

Dynamic Condition

Power is consumed when the input changes state for two main reasons:

1. The conducting transistor must charge or discharge the total output capacitance $C_L$.

2. During the brief transition interval, both transistors can be partially ON, creating a short-circuit current pulse from supply to ground.

The dominant first-order capacitive-power relation is

$$\boxed{P_{dyn}\approx \alpha C_LV_{SS}^{2}f+P_{sc}},$$

where $\alpha$ is the switching-activity factor, $f$ is the clock or event frequency, and $P_{sc}$ is the short-circuit component.

Note

Exam Summary

• Stable input: one transistor ON, the other OFF; static power is nearly zero except for leakage.

• Changing input: the output capacitance charges or discharges, and both devices may conduct briefly; dynamic power is non-zero.

• Logic action: LOW input gives HIGH output, while HIGH input gives LOW output.